Arithmetic computation of potential addresses

#1. Field of the Invention

#This invention relates in general to the field of instruction execution in computers, and more particularly to an apparatus in a pipeline microprocessor for providing speculative address operands to address-dependent micro instructions.

#2. Description of the Related Art

#These and other objects, features, and advantages of the present invention will become better understood with regard to the following description, and accompanying drawings where:

#FIG. 1 is a block diagram illustrating stages of a related art pipeline microprocessor.

#FIG. 2 is a table illustrating execution of an address-dependent micro instruction by the microprocessor of FIG. 1, where an operand required by the address-dependent micro instruction is a result of an arithmetic operation prescribed by a preceding micro instruction.

#In light of the above background on techniques for executing program instructions in a pipeline microprocessor, several related art examples will now be discussed with reference to FIGS. 1 and 2. These examples highlight the problems encountered in a pipeline microprocessor when an address-dependent micro instruction immediately requires the result of a preceding micro instruction, where the result has not yet been generated by the preceding micro instruction. More specifically, in this situation the address-dependent micro instruction must be stalled in the pipeline until the preceding micro instruction is executed to the point that the result is generated. Following this discussion, a detailed description of the present invention will be provided with reference to FIGS. 3 through 6. The present invention provides an apparatus that computes and stores speculative address operands resulting from arithmetic operations prior to execution of the instructions prescribing the arithmetic operations, thereby allowing address-dependent micro instructions to access these operands without experiencing a stall.

#Referring to FIG. 1, a block diagram is presented illustrating stages of a related art pipeline microprocessor 100. The microprocessor 100 includes a fetch stage 101, translate stage 102, register stage 103, address stage 104, load stage 105, align stage 106, execute stage 107, store stage 108, and write back stage 109. The microprocessor also has interlock logic 110 coupled to each of the pipeline stages 101-109.

#In operation, the fetch stage 101 retrieves macro instructions from external memory (not shown) that are to be executed by the microprocessor 100. The translate stage 102 translates, or decodes, the fetched macro instructions into associated micro instructions. The register stage 103 retrieves operands specified by the micro instructions from a register file (not shown) for use by logic (not shown) within subsequent stages 104-109 of the pipeline. The address stage 104 generates memory addresses specified by the micro instructions to be used in data storage and retrieval operations. The load stage 105 reads data from the external memory to access memory operands using the addresses generated in the address stage 104. The align stage 106 extracts the memory operands from the data and aligns the memory operands for execution. The execute stage 107 performs arithmetic, logical, or other prescribed operations to generate results using the operands retrieved from the register file and/or memory. The store stage 108 writes the results generated by the execute stage 107 or the operands retrieved from the register file to external memory at the memory addresses calculated by logic in the address stage 104. The write back stage 109 updates registers in the register file with the results generated in the execute stage 107 or with operands retrieved from memory by the load stage 105. Micro instructions proceed in sequence through each successive stage of the pipeline in synchronization with a pipeline clock signal (not shown). To achieve optimum pipeline performance, while a given micro instruction is executing in a given stage of the pipeline, a preceding micro instruction should be executing in a subsequent pipeline stage and a following micro instruction should be executing in a previous pipeline stage. In other words, during any given clock cycle, all stages 101-109 of the microprocessor 100 should be performing their architected functions; no stage should be idle.