Digital signal processor architecture for high computation speed

Abstract

A digital signal processor includes an instruction fetch unit for fetching and decoding instructions, a data cache, a memory, an execution unit, including a register file, for executing the instructions, and a load control unit for loading data from the data cache to the register file in response to instructions of a first instruction type and for loading data from the memory to the register file in response to instructions of a second instruction type. Instructions of the first instruction type may be microcontroller instructions, and instructions of the second instruction type may be digital signal processor instructions. The execution unit may include a microcontroller execution unit having a first number of pipeline stages for executing the microcontroller instructions and a digital signal processor execution unit having a second number of pipeline stages for executing the digital signal processor instructions.

Dependencies are inferred from the claim text.