Memory device for transferring streams of data

An integrated memory circuit for storing and providing streams of data, said integrated memory circuit accommodating serial access and limited random access, and said integrated memory circuit comprising:

• a random access memory array having an address input, a data input port, and a data output port;
• a first data buffer having a data port coupled to said memory array data input port, said first data buffer synchronizing operation of said memory array to the stored stream of data;
• a second data buffer having a data port coupled to said memory array data output port, said second data buffer synchronizing operation of said memory array to the provided stream of data;
• and
• first and second address generators wherein said first address generator generates addresses used for writing the stored data stream into said memory array, said second address generator generates addresses used for reading the provided data stream from said memory array, and each of said first and second address generators comprises:
• a binary counter having an output coupled to said memory array address input and a data input, said binary counter being for counting memory addresses to be applied to said memory array;
• and
• a serially loaded address buffer register having an output coupled to said binary counter data input, said address buffer register being for supplying an initial random access memory address which starts the count of said binary counter.

A method of storing and providing streams of data using a random access memory array, said method comprising the steps of:

• buffering the streams of data into and out from the memory array so that the stored and provided data streams occur asynchronously with operation of the memory array;
• generating a random access address;
• and
• generating a sequence of addresses initialized with said random access address said addresses being successively applied to the random access memory array.