US 2003/0196067 A1 · RAM with fewer address terminals than data terminals

Abstract

A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Drawings

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Drawings

Claims19

Dependent claims

A memory circuit for storing and providing streams of data, said memory circuit accommodating both serial access and random access, and said memory circuit comprising:

a random access memory array having an address input and a data port;
a data buffer having a data port coupled to said memory array data port, said data buffer synchronizing operation of said memory array to the streams of data;
an address sequencer having a data input and having an output coupled to said memory array address input, said address sequencer generating a sequence of memory addresses to be successively applied to said memory array;
and
an address buffer register having an output coupled to said address sequencer data input, said address buffer register supplying a random access address that initializes the sequence of memory addresses generated by said address sequencer.

2 more elements

An integrated memory circuit for storing and providing streams of data, said integrated memory circuit accommodating serial access and limited random access, and said integrated memory circuit comprising:

a random access memory array having an address input, a data input port, and a data output port;
a first data buffer having a data port coupled to said memory array data input port, said first data buffer synchronizing operation of said memory array to the stored stream of data;
a second data buffer having a data port coupled to said memory array data output port, said second data buffer synchronizing operation of said memory array to the provided stream of data;
and
first and second address generators wherein said first address generator generates addresses used for writing the stored data stream into said memory array, said second address generator generates addresses used for reading the provided data stream from said memory array, and each of said first and second address generators comprises:
a binary counter having an output coupled to said memory array address input and a data input, said binary counter being for counting memory addresses to be applied to said memory array;
and
a serially loaded address buffer register having an output coupled to said binary counter data input, said address buffer register being for supplying an initial random access memory address which starts the count of said binary counter.

5 more elements

Dependencies are inferred from the claim text.

Description6,131 words

Summary575 words

#The present invention relates in general to digital memory circuits. Specifically, the present invention relates to digital memory circuits which have particular advantages when used in connection with video applications.

#Digital TV, VCR, and related video applications often utilize a frame or field memory that stores pixels which together represent an entire frame of video. Such a frame memory is used in producing a variety of special effects, such as frame freezing, zoom, pan, split screen monitoring, and the like. Although a frame memory may be constructed using conventional discrete integrated circuits, such a frame memory is relatively expensive, dissipates an undesirably large amount of power, and occupies an undesirably large amount of space. When such a frame memory is targeted for use in a commercial product, these problems are major ones. Accordingly, a single integrated circuit, either alone or in combination with as few other integrated circuits as possible, improves upon a frame memory which has been constructed from conventional discrete integrated circuits.

#Prior art integrated circuit devices have attempted to address the frame memory problem. However, such devices fail to provide an architecture which adequately addresses video application needs. For example, devices which include only a few of the typically needed frame memory functions may be used in providing a wide variety of special effects. However, they must be combined with such a large quantity of conventional discrete integrated circuits that little improvement results over constructing a frame memory entirely from conventional discrete integrated circuits. On the other hand, a conventional frame memory integrated circuit may include a random access memory with complete on-chip address calculation. A video application which utilizes such a frame memory accesses the entire frame memory serially. Thus, frame freeze and split screen monitoring special effects are supported. However, zoom and pan functions are either impossible or impractical using such a device.

Brief description of the drawings5 figures

#A more complete understanding of the present invention may be derived by referring to the detailed description and claims when considered in connection with the accompanying drawings, in which like reference numbers indicate like features throughout the drawings, and wherein:

#FIG. 1 illustrates a frame of a video display screen with which the present invention may be used;

#FIG. 2 shows a block diagram of a memory circuit built according to the teachings of the present invention;

Detailed description5,382 words

#FIG. 1 illustrates a video frame 10, such as may appear on a TV tube or other video display terminal. Although frame 10 may appear as a continuous analog video picture to a viewer, frame 10 may be electrically represented as a multiplicity of digitized pixels 12. Each one of the pixels defines parameters, such as color and relative intensity, for one of a multiplicity of very small dot areas within the picture of frame 10. Accordingly, the video frame 10 may contain a relatively large number of the digitized pixels 12. For example, a frame containing 488 columns of pixels 12 by 488 rows of pixels 12 has a total of 238,144 pixels per frame.

#Pixels 12 are typically transmitted or otherwise processed in a predetermined sequential order to preserve the spatial relationship between the pixels 12. For example, in a conventional raster scan application, pixels 12 may be transmitted to a memory device for storage or from storage in a memory device to a video display in successive order beginning with a pixel 12a, that represents the pixel 12 in the first column of the first row of frame 10, and continuing in successive order to a pixel 12b, which represents the pixel 12 in the last column of the first row of frame 10. Immediately following the transmission of pixel 12b and sync information (not shown), a pixel 12c, which represents the pixel 12 in the first column of the second row, may be transmitted followed in successive order by the remaining pixels 12 contained in the second row of frame 10. Transmission of pixels 12 continues in this fashion until a pixel 12d, which represents the pixel 12 in the last column of the last row of frame 10, has been transmitted. Thus, any processing device which knows the timing relationship between an arbitrarily located pixel 12 and the beginning pixel 12a also knows or can easily calculate the spatial location of such arbitrarily located pixel 12 within frame 10.

#A digital TV, VCR, or the like may contain a large frame or field memory which is capable of storing all of the pixels 12 within frame 10. Pixels 12 collectively appear as a serial data stream when they are applied to the frame memory. Except for special effects, the relative order of pixels 12 in this serial data stream must generally be preserved when they are read from the frame memory to preserve the spatial relationships between the pixels 12. Some special effects do not require this preserved order, and valuable computation time may be wasted by precisely preserving the order of the pixels 12 as the pixels 12 are being read from the frame memory.

Facts

Application

10/452,339Filed 2 Jun 2003

Priority

23 Dec 1987

Published

16 Oct 2003

Term ends

Not estimatedThe source records don’t support an estimate.

Classification9 codes

G09G 5/391
Control of the bit-mapped memory: resolution modifying circuits, e.g. variable screen formats
G11C 7/103
Read-write modes for single port memories, i.e. having either a random port or a serial port: using serially addressed read-write data registers
G11C 7/1036
Read-write modes for single port memories, i.e. having either a random port or a serial port: using data shift registers
G11C 7/1072
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: for memories with random access ports…

Family

Application07/137,305Continuation · filed 23 Dec 1987

Application07/512,611Division · filed 20 Apr 1990

Application07/512,611Continuation · filed 20 Apr 1990

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Application08/175,478Division · filed 29 Dec 1993

Application08/175,478Continuation · filed 29 Dec 1993

Application08/362,289Division · filed 22 Dec 1994

Application08/488,231Division · filed 7 Jun 1995

Application09/745,892Division · filed 21 Dec 2000

Application10/190,017Division · filed 5 Jul 2002