System and method for translation buffer accommodating multiple page sizes

#The present invention relates generally to computer systems having virtual memory addressing, and in particular the present invention relates to such computer systems have a translation lookaside buffer (TLB) or similar cache for use with virtual memory addressing.

#Virtual memory addressing is a common strategy used to permit computer systems to have more addressable memory than the actual physical memory installed within a given computer system. Data is stored on a storage device such as a hard disk drive and is loaded into physical memory as needed typically on a memory page-by-memory page basis, where a memory page is a predetermined amount of contiguous memory. Computer systems having virtual memory addressing must translate a given virtual memory address to a physical memory address that temporarily corresponds to the virtual address.

#In many such computer systems, translation is accomplished via a translation lookaside buffer (TLB), also known by those skilled in the art as a TC (translation cache). The TLB is a cache located preferably near the processor of the computer system in order to improve the access speed and also holds virtual page-to-physical page mappings most recently used by the processor. The TLB entries may be cached entries from a page table or translations created and/or inserted by the operating system. The translation of virtual to physical addresses commonly are a critical path in computer performance. Conventional TLB organizations well-known to those skilled in the art include direct-mapping in which an entry can appear in the TLB in only one position, fully associative mapping in which an entry can be placed anywhere in the TLB, and set-associative in which an entry can be placed in a restricted set of places in the TLB where a set is a group of entries in the cache and an entry can be placed anywhere within the set.

#FIG. 1 is a block diagram of a computer system of an embodiment of the invention.

#FIG. 2 is a block diagram of a virtual address word using a 4K page size.

#FIG. 3 is a block diagram of a virtual address word using a 256K page size.

#In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the inventions may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the claims.

#The present invention describes a translation lookaside buffer TLB, or similar cache, with the ability to translate addresses according to pages of varying sizes, for computer systems having virtual memory addressing. The invention is not particularly limited to a given computer system. Both scalar and vector computer systems, as well-known within the art, can be used in the invention.

#Referring to FIG. 1, a block diagram of a computer system 100 of an embodiment of the invention is shown. There may be more than one processor 110, as commonly found in parallel architectures, for example. The computer system 100 employs virtual memory addressing so that it has more addressable memory than the actual physical memory installed. Processor 110 must therefore translate a given virtual memory address 120 to a physical memory address 125 within data space 130 that resides in physical memory that temporarily corresponds to the virtual address 120. As known within the art, in a virtual memory addressing architecture, data may be stored on a storage device such as hard disk drive (HDD) 140, and loaded into data space 130 located in physical memory as needed.