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AssigneeRambus Inc.
InventorsRamprasad Satagopan, Richard M. Barth
Estimating the term…
A memory controller for a high-performance memory system has a pipeline architecture for generating control commands which satisfy logical, timing, and physical constraints imposed on control commands by the memory system. The pipelined memory controller includes a bank state cache lookup for determining a memory bank state for a target memory bank to which a control command is addressed, and a hazard detector for determining when a memory bank does not have a proper memory bank state for receiving and processing the control command. The hazard detector stalls the operation of the control command until the memory bank is in a proper state for receiving and processing the control command. The memory controller also has a command sequencer which sequences control commands to satisfy logical constraints imposed by the memory system, and a timing coordinator to time the communication of the sequenced control commands to satisfy timing requirements imposed by the memory.
A pipelined memory controller for use in a memory system having a memory device connected to the memory controller, the memory controller comprising:
A pipelined memory controller for receiving memory access requests and in response thereto controlling access to a memory device in a memory system, comprising:
Dependencies are inferred from the claim text.
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With latency improvement: using a concurrent pipeline structrure
Computing and data processing
Term end not estimated
This invention pertains to the field of memory controllers, and more particularly, to a memory controller having a pipelined architecture for controlling access to memory devices in a memory system using an open-page policy, wherein memory pages within a memory device are not closed after each memory access.
Typically, a semiconductor memory system comprises one or more memory devices connected by means of a bus to a memory controller which manages data flow to and from the memory devices. The memory devices may be dynamic random access memory (DRAM) devices, static random access memory (SRAM), etc.
FIG. 1 illustrates the organization of an exemplary memory device 100. The memory device 100 comprises a plurality of memory banks 110. Each memory bank 110 in turn comprises a plurality of memory pages 120 and each memory page 120 comprises a plurality of memory cells 130. The memory pages 120 within each memory bank 110 share a common pair of sense amplifier arrays 140 which are used to sense data stored within the memory cells 130 in the memory bank 110. The total number of memory cells 130 within a memory page 120 is referred to as the “page size.”
FIG. 1 shows an arrangement of memory cells within a memory device.
FIG. 2 is a block diagram of a memory system wherein a pipelined memory controller according to one or more aspects of the present invention may operate.
FIG. 3 shows an arrangement of memory banks in a memory device which may be used in a memory system with a pipelined memory controller according to one or more aspects of the present, invention.
The present invention provides a pipelined memory controller which addresses the logical, timing, and physical constraints discussed above. In one aspect, the present invention is well adapted for incorporation in emerging high speed memory systems. The assignee of the present invention has pioneered the development of next generation memory systems having a relatively narrow, high speed bus(es) and associated memory devices, along with the interface technology required to provide high data throughput. See, U.S. Pat. Nos. 5,319,755; 5,243,703; and 5,254,883, the disclosures of which are incorporated herein by reference.
In addition to the referenced U.S. patents, information describing the assignee's memory systems and memory devices may be had at Rambus™ Inc., Mountain View, Calif. See, for example, the Direct RDRAM™ 64/72-Mbit Data Sheet, the Direct RAC Data Sheet, the Direct RMC.dl Data Sheet, A Logical View of the Direct Rambus Architecture, Direct Rambus Technology Overview, Direct Rambus Clock Generator Source Sheet, Direct Rambus RIMM™ Module Data Sheet, the Direct Rambus Memory controller Summary, all 1998 documents and all incorporated herein by reference.
Turning specifically to the present invention, FIG. 5 is a functional block diagram illustrating an architecture for a pipelined memory controller 500 which generates and issues control commands to memory devices. The pipelined memory controller 500 may operate as the memory controller 230 shown in the memory system 200 of FIG. 2. In this case, the pipelined memory controller 500 receives memory access requests from one or more processors, and generates control commands which it issues to target memory devices 210 in the memory system 200 to satisfy the memory access requests.