Memory system for supporting multiple parallel accesses at very high frequencies

#This invention relates to computer memory systems and, more particularly, to pipelined memory systems that support multiple accesses at very high frequencies. The memory systems are particularly useful in digital signal processing systems, but are not limited to such applications.

#A digital signal computer, or digital signal processor (DSP), is a special purpose computer that is designed to optimize performance for digital signal processing applications, such as, for example, fast Fourier transforms, digital filters, image processing, signal processing in wireless systems and speech recognition. Digital signal processor applications are typically characterized by real-time operation, high interrupt rates and intensive numeric computations. In addition, digital signal processor applications tend to be intensive in memory access operations and require the input and output of large quantities of data. Digital signal processor architectures are typically optimized for performing such computations efficiently.

#Microcontrollers, by contrast, involve the handling of data but typically do not require extensive computation. Architectures that are optimized for DSP computations typically do not operate efficiently as microcontrollers, and microcontrollers typically do not perform well as digital signal processors. Nonetheless, applications frequently require both digital signal processor and microcontroller functionality.

#For a better understanding of the present invention, reference is made to the accompanying drawings, which are incorporated herein by reference and in which:

#FIG. 1 is a block diagram of an embodiment of a digital signal processor suitable for incorporation of the invention;

#FIG. 2 is a block diagram of the digital signal processor of FIG. 1, showing major components of each pipeline unit;

#A block diagram of an embodiment of a digital signal processor suitable for incorporation of the invention is shown in FIGS. 1 and 2. The digital signal processor includes a computation core 10 and a memory 12. The computation core 10 is the central processor of the DSP. Both the core 10 and the memory 12 are pipelined, as described below. Core 10 includes an instruction fetch unit 20, a data address generator 22, a load/store unit 24, a data cache 26, a register file 28, a microcontroller execution unit 30, a DSP execution unit 32 and a data cache controller 34.

#Instruction fetch unit 20 may include a 32 k byte instruction cache 50, branch prediction circuitry 52, a TLB (translation look-aside buffer) 54, an instruction alignment unit 56 and an instruction decoder 58. In instruction fetch unit 20, program instructions are fetched from the instruction cache 50 and are decoded by the instruction decoder 58. In the event of an instruction cache miss, the requested instruction is accessed in memory 12. Instructions may be placed in an instruction queue and subsequently decoded by the instruction decoder 58.

#The data address generator 22 may include loop buffers 70 and adders 72 for data address generation in program loops. Virtual addresses are translated to physical addresses in data address generator 22. Data address generator 22 may also include a P register file 74, a future file 76, hazard detection circuitry 78 and a TLB 80.