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US 2003/0196057 A1Published application
Semiconductor memory device having control circuit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorMasaki Tsukude
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AssigneeMitsubishi Denki Kabushiki Kaisha
InventorMasaki Tsukude
Estimating the term…
Term end not estimated
In a freeze reset circuit in a semiconductor memory device, when a row act signal is not activated in a predetermined period determined by a trailing edge delay circuit after a chip enable signal is set to the H level during a write or read operation, a freeze reset signal is output from a logic gate after a predetermined period. As a result, the semiconductor memory device terminates the write or read operation. Therefore, the semiconductor memory device can ensure the stability of the write or read operation.
A semiconductor memory device having an operation state capable of performing a read operation and a write operation of data and a standby state to hold said data, comprising:
Dependencies are inferred from the claim text.
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Forming cells needing refreshing or charge regeneration, i.e. dynamic cells: management or control of the refreshing or charge-regeneration cycles
Static stores
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1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a dynamic semiconductor memory device capable of performing a refresh operation independently of input signals from the outside (which will be referred to as a “complete-hidden-refresh-function-included DRAM” hereinafter).
2. Description of the Background Art
FIG. 1 shows a whole structure of a complete-hidden-refresh-function-included DRAM in a first embodiment of the present invention.
FIG. 2 is a circuit diagram showing a structure of a state control circuit shown in FIG. 1.
FIG. 3 is a timing chart showing a read or write operation of the state control circuit shown in FIG. 2.
Embodiments of the present invention will be described in detail with reference to the drawings. The same characters in the drawings indicate the same or corresponding portions, and the descriptions thereof will not be repeated.
[First Embodiment]
FIG. 1 shows a whole structure of a complete-hidden-refresh-function-included DRAM in a first embodiment of the present invention.