Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors

#The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs using a 1-hot vector tag plus valid bit protection scheme and/or a 2-hot vector tag protection scheme in high speed memories, such as caches.

#Modern high-performance processors, for example, Intel® Architecture 32-bit (IA-32) processors, include on-chip memory buffers, called caches, to speed up memory accesses. IA-32 processors are manufactured by Intel Corporation of Santa Clara, Calif. These caches generally consist of a tag array and a data array. The data array generally stores the data that is needed during the execution of the program. The tag array generally stores either a physical address or a virtual address of the data as tags. For reliability reasons, these stored tags are often protected for error detection by associating a separate parity bit with each tag. In even higher performance processors, for example, Intel® Architecture 64-bit (IA-64) processors, each tag is generally stored as a 1-hot vector in a 1-hot cache, which is derived during a Translation Look-aside Buffer (TLB) lookup for an address translation. IA-64 processors are manufactured by Intel Corporation of Santa Clara, Calif. A “1-hot vector” is an n-bit, binary address in which a single bit is set to specify a matching address translation entry in the TLB. The advantage of using a 1-hot vector as a tag is that it improves the operating frequency of a cache. Unfortunately, the protection of these 1-hot vectors presents a great challenge since the conventional parity bit protection scheme used to protect the standard tag in the conventional cache does not work well for the 1-hot vectors. For example, when an entry in the TLB is replaced, all of the tags with the corresponding 1-hot vectors in the 1-hot cache must be invalidated. This invalidation can be performed using a blind invalidate operation, in which all 1-hot vectors in the cache with the “1” bit matching the selected TLB entry will be invalidated. However, since the blind invalidate operation only overwrites the 1-hot vector and not the associated parity bit, the associated parity bit is no longer valid for the new value in the 1-hot vector. In addition, in the 1-hot cache, since all of the cleared bits are now zero, if any of the bits are changed by a soft error to a 1, then, the cleared entry becomes a 1-hot vector, which is indistinguishable from a real, valid 1-hot vector that also may be stored in the 1-hot cache. A “soft” error is an error that occurs when a bit value that is set to a particular value in the processor is changed to an opposite value by, for example, an alpha particle bombardment and/or gamma-ray irradiation of the bit.

#A straight forward protection scheme for the 1-hot tag cache that does work for the 1-hot vectors involves having a second tag array to maintain a duplicate copy of the 1-hot vectors in the tag array. However, although this duplicate tag array scheme works, it requires a larger chip area and a high timing impact to implement.

#FIG. 1 is a logic block diagram of a 1-hot tag cache, in accordance with an embodiment of the present invention.

#FIG. 2 is a circuit schematic diagram of a known 1-hot tag memory cell, illustrating how the 1-hot tag cache operates with no interaction between the memory bit circuits in the 1-hot tag memory cell.

#FIG. 3 is a circuit schematic diagram of a 1-hot tag plus valid bit memory cell, illustrating the interaction between the memory bit circuits in the 1-hot tag plus valid bit memory cell, in accordance with an embodiment of the present invention.

#In accordance with embodiments of the present invention, circuits and methods to protect the 1-hot vectors used in the tag cache are described herein. As a way of illustration only, two embodiments of the present invention are described: a 1-hot plus valid bit and a 2-hot vector scheme, however, these two embodiments should not be taken to limit any alternative embodiments, which fall within the spirit and scope of the appended claims.

#In general, a cache that stores 1-hot vectors as tags is referred to as a 1-hot tag cache and a cache that stores 2-hot vectors as tags is referred to as a 2-hot tag cache. A 1-hot vector is an n-bit string that contains a single “1” and n−1 “0's”, for example, “00001000” is an eight-bit 1-hot vector. Similarly, a 2-hot vector is an n-bit string that contains two consecutive “1's” and n−2 “0's”, for example, “00011000” is an eight-bit 2-hot vector. The right most “1” bit in a 2-hot vector is called a primary bit and a left neighbor “1” bit of the primary bit is called an aux (auxiliary) bit.

#FIG. 1 is a logic block diagram of a known implementation of a 1-hot tag cache 119. The 1-hot tag cache 119 shown in FIG. 1 is a 4-way set associative cache, which means that four tags are stored for any given set (row) in the cache. In FIG. 1, the 1-hot tag cache 119 is coupled to a TLB 109, which includes a TLB virtual address array 110. The 1-hot tag cache 119 includes a 1-hot tag array 120, a cache data array 125, comparators 130-133, a first multiplexer 140, and a second multiplexer 150.