Share masks and alias for directory coherency

#The invention relates to computer processors and memory systems. More particularly, the invention relates to optimizing coherent memory access operations within multiprocessor computer systems having distributed shared memory architectures.

#Multiprocessor, or parallel processing, computer systems rely on a plurality of microprocessors to handle computing tasks in parallel to reduce overall execution time. One common implementation of a multiprocessor system is the “single bus architecture, in which a plurality of processors are interconnected through a single bus. However, because of the limited bandwidth of the single bus also limits the number of processors that can be interconnected thereto, recently a networked multiprocessor systems have also been developed, which utilize processors or groups of processors connected to one another across an interconnection fabric, e.g., a network, and communicating via “packets” or messages.

#Typically, in a networked multiprocessor system includes a plurality of nodes or clusters interconnected via a network. For example, FIG. 1 shows an exemplary networked multiprocessor system 100, in which a plurality of nodes 102 are interconnected to each other via the interconnection fabric 101, e.g., a network. By way of an example, only two nodes are shown. However, the networked multiprocessor system 100 may have any number of nodes. Moreover, although, in FIG. 1, the interconnection fabric 101 is shown to provide interconnections only between the nodes 102, all system entities, including the cells 103, the processors 105 and the memories 104, are interconnected, and communicate, with the rest of the system through the interconnection fabric 101.

#Features and advantages of the present invention will become apparent to those skilled in the art from the following description with reference to the drawings, in which:

#FIG. 1 is a block diagram of the relevant portions of an exemplary conventional networked multiprocessor distributed memory system;

#FIG. 2A is an illustrative table showing relevant portions of an exemplary embodiment of the directory tag bits of a cache line, for the case in which the cache line is idle, in accordance with the principles of the embodiment of the present invention;

#For simplicity and illustrative purposes, the principles of the present invention are described by referring mainly to an exemplar embodiment thereof. However, one of ordinary skill in the art would readily recognize that the same principles are equally applicable to, and can be implemented in, a multiprocessor shared memory system having a different implementation or architecture, and that any such variation would be within such modifications that do not depart from the true spirit and scope of the present invention.

#For example, while much of the following description of the present invention makes references to multiprocessor systems, it should be appreciated that the concept of distributing tasks between processors in multiprocessor systems may also be applied to distributed computer systems which distribute tasks between different computers in a networked environment (e.g., a LAN or WAN). Further, many of the functions and problems associated with multiprocessor and distributed computer systems are quite similar and equally applicable to both types of systems. Consequently, the term “networked computer system” will be used hereinafter to describe both systems in which the nodes are implemented as individual microprocessors or groups of processors (multiprocessor systems) or as individual computers which may separately utilize one or more processors (distributed computer systems).

#Moreover, the present invention is described with reference to a particular implementation in which there are a particular number of processors for each cell, a particular number of cells per node, etc. However, it should be apparent to those having an ordinary skill that the system described herein may have any number of processors and cells, and that any such variation would be within such modifications that do not depart from the true spirit and scope of the present invention.