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US 2003/0196045 A1Published application
Processing device which prefetches instruction having indicator bits specifying a quantity of operand data for prefetching
AssigneeHitachi, Ltd.
InventorsKenji Matsubara, Toshihiko Kurihara, Hiromitsu Imori
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Abstract
For improving the performance of an information processing unit having caches, indication bits for indicating a hierarchical level of a cache to which an operand data is to be transferred or for indicating a quantity of an operand data to be transferred or for indicating both are provided in a software prefetch instruction, and at the time of a transfer of block data or line data, a required data is transferred to a cache based on the indication bits in the prefetch instruction.
Claims3
A processing device for controlling two hierarchical level data caches, comprising:
- a processor which executes a prefetch instruction included as one of a plurality of instructions of a program in a main memory which is external of aid processing device;
- a memory interface unit which accesses said main memory;
- an internal cache controlled as a first level cache;
- and
- a cache control function which controls an external cache external of said processing device as a second level cache,
- wherein said prefetch instruction, when executed causes said processor to perform a prefetch operation by transferring operand data to be used in a subsequent load instruction form said main memory to said external cache and/or said internal cache, prior to executing said subsequent load instruction, and
- wherein said prefetch instruction includes at least one indication bit for specifying cache levels to which said operand data is to be transferred, said at least one indication bit being included in an operation part of said prefetch instruction.
4 more elements
Dependencies are inferred from the claim text.