Cache-line reuse-buffer

#This invention generally relates to cache memories. More particularly, an aspect of this invention relates to a cache-line reuse-buffer.

#A cache is generally a small fast memory holding recently accessed data, designed to speed up subsequent access to the same data. Instructions and data are transferred from main memory to the cache in blocks, using a look-ahead algorithm. The cache stores this information in one or more cache lines. Typically, sequential lines of instructions are stored in the cache lines. A fetch engine system speculatively stores consecutive sequential lines of instructions in anticipation of their future use.

#FIG. 1 illustrates a prior art fetch engine system fetching a new cache line from the instruction cache every fetch cycle. The fetch engine system consists of a BTB engine, a branch predictor (BP), a return address stack (RAS), logic to determine the next address, and an instruction cache. The fetch engine fetches one full block of instructions from the instruction cache per cycle by accessing the instruction cache. The BTB engine and branch predictor (BP) provide instruction information of the current fetch cycle. The logic to determine the next address provides the next fetch address. The instruction cache consists of multiple cache lines. Note, the at sign “@” means “address.

#The drawings refer to the invention in which:

#FIG. 1 illustrates a prior art fetch engine system fetching a new cache line from the instruction cache every fetch cycle;

#FIG. 2 illustrates a block diagram of an embodiment of the cache-line reuse-buffer to store a cache line from an instruction cache;

#While the invention is subject to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will herein be described in detail. The invention should be understood to not be limited to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

#In the following description, numerous specific details are set forth, such as examples of specific data signals, named components, connections, number of bytes in a cache line, etc., in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well known components or methods have not been described in detail but rather in a block diagram in order to avoid unnecessarily obscuring the present invention. Further specific numeric references such as first starting address, may be made. However, the specific numeric reference should not be interpreted as a literal sequential order but rather interpreted that the first starting address is different than a second starting address. Thus, the specific details set forth are merely exemplary. The specific details may be varied from and still be contemplated to be within the spirit and scope of the present invention. The term coupled is defined as meaning connected either directly or indirectly.

#In general, various methods, apparatuses, and systems are described that compare a current fetch request having a first start address and length associated with the current fetch request to a second start address of the next fetch request, determine whether the content already loaded in a buffer will be used to at least partially fulfill the next fetch request based upon the comparison, and inhibit access to an instruction cache based upon the comparison.