Eliminating unnecessary data pre-fetches in a multiprocessor computer system
AssigneeInternational Business Machines Corporation
InventorFarnaz Toussi
Life of this patent
Estimating the term…
Abstract
A multiprocessor computer system employs a number of levels of cache memories with each processor. A cache controller for a lower level cache memory receives a memory block pre-fetch request which requests a particular memory block. The cache controller determines a likelihood that the particular memory block will be invalidated prior to use of the memory block by a processor which issued the pre-fetch request. Based on that determination, the cache controller determines whether to honor the pre-fetch request.
Claims16
A method of operating a multiprocessor computer system, the method comprising:
- (a) receiving a memory block pre-fetch request which requests a particular memory block;
- (b) determining a likelihood that the particular memory block will be invalidated prior to use of the particular memory block by a processor which issued the request;
- and
- (c) determining whether to fulfill the request based on a result of step (b).
The method of step 2, wherein the request is not fulfilled when the state of the particular memory block is determined to be shared read-write.
A method of operating a multiprocessor computer system, the method comprising:
- (a) receiving a memory block pre-fetch request which requests a particular memory block;
- (b) determining a state of the particular memory block;
- and
- (c) determining whether to fulfill the request based on a result of step (b).
A multiprocessor computer system, comprising:
- a plurality of processors operatively coupled to each other;
- a respective plurality of cache memories associated with each of the processors and including a high level cache memory and at least one lower level cache memory;
- and
- a respective cache controller associated with each lower level cache memory;
- wherein each cache controller includes:
- means for receiving a memory block pre-fetch request which requests a particular memory block;
- likelihood determining means for determining a likelihood that the particular memory block will be invalidated prior to use of the particular memory block by the associated processor;
- and
- request determining means, responsive to the likelihood determining means, for determining whether to fulfill the pre-fetch request.
A multiprocessor computer system, comprising:
- a plurality of processors operatively coupled to each other;
- a respective plurality of cache memories associated with each of the processors and including a high level cache memory and at least one lower level cache memory;
- and
- a respective cache controller associated with each lower level cache memory;
- wherein each cache controller includes:
- means for receiving a memory block pre-fetch request which requests a particular memory block;
- state determining means for determining a state of the particular memory block;
- and
- request determining means, responsive to the state determining means, for determining whether to fulfill the pre-fetch request.
Dependencies are inferred from the claim text.