Cache system
AssigneeSTMicroelectronics S.r.l.
InventorsAndrew Craig Sturges, David May
Life of this patent
Estimating the term…
Abstract
A cache system is provided which includes a cache memory and a cache refill mechanism which allocates one or more of a set of cache partitions in the cache memory to an item in dependence on the address of the item in main memory. This is achieved in one of the described embodiments by including with the address of an item a set of partition selector bits which allow a partition mask to be generated to identify into which cache partition the item may be loaded.
Claims15
A cache system for operating between a processor and a main memory of a computer, the cache system comprising:
- a cache memory having a set of cache partitions, each cache partition comprising a plurality of addressable storage locations for holding items fetched from said main memory for use by the processor;
- a cache refill mechanism arranged to fetch an item from the main memory and to load said item into the cache memory at one of said addressable storage locations;
- and
- a cache partition mask generator which generates from a partition selector associated with the address of an item to be cached a multi-bit partition mask identifying into which cache partition the item may be loaded so that the cache refill mechanism is operable to allocate to each said item fetched from the main memory one of said cache partitions in dependence on the address of said item in the main memory.
A cache system according to any preceding claim, wherein each address in main memory comprises a page number and an offset.
A cache system according to any preceding claim, wherein one or more cache partitions is allocated to a page in main memory.
A cache system according to any preceding claim, comprising a cache access circuit which accesses items from the cache memory according to the addresses in main memory of said items and regardless of the cache partition in which the item is held in the cache memory.
A method of operating a cache memory arranged between a processor and a main memory of a computer, wherein, when the processor requests an item from main memory using an address in main memory for said item and that item is not held in the cache memory, said item is fetched from the main memory and loaded into one of a plurality of addressable storage locations in the cache memory, the addressable storage locations being arranged as a set of cache partitions and wherein each address includes a multi-bit partition selector identifying into which cache partition the item may be loaded so that one of said cache partitions is allocated to said item in dependence on the address of said item in main memory.
A cache system for operating between a processor and a main memory of a computer, the cache system comprising:
- a cache memory having a set of cache partitions, each cache partition comprising a plurality of addressable storage locations for holding items fetched from said main memory for use by the processor;
- and
- a cache refill mechanism arranged to fetch an item from the main memory and to load said item into the cache memory at one of said addressable storage locations, wherein the cache refill mechanism is operable to allocate to each said item fetched from the main memory one or more of said cache partitions in dependence on the address of said item in the main memory.
Dependencies are inferred from the claim text.