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US 2003/0196038 A1Published application
Semiconductor integrated circuit
AssigneeMatsushita Elec. Ind. Co. Ltd.
InventorMasaya Sumita
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AssigneeMatsushita Elec. Ind. Co. Ltd.
InventorMasaya Sumita
Estimating the term…
It is an object of the present invention to provide a semiconductor integrated circuit having a chip layout that reduces line length to achieve faster processing. A cache comprises a TAG memory module and a cache data memory module. The cache data memory module is divided into first and second cache data memory modules which are disposed on both sides of the TAG memory module, and input/output circuits of a data TLB are opposed to the input/output circuit of the TAG memory module and the input/output circuits of the first and second cache data memory modules across a bus area to reduce the line length to achieve faster processing.
A semiconductor integrated circuit including a cache capability provided by a Translation Look-aside Buffer (TLB) and a cache, wherein
A semiconductor integrated circuit including a cache capability provided by a translation look-aside buffer (TLB) and a cache, wherein
A semiconductor integrated circuit including cache memory comprising a plurality of data memory modules, wherein
Dependencies are inferred from the claim text.
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Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: caches…
Address translation: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: using…
Associated with a data cache: the data cache being concurrently physically addressed
Term end not estimated
The present invention relates to a semiconductor integrated circuit and in particular to a one-chip large-scale integrated circuit having cache capability.
A one-chip large-scale integrated circuit (LSI) containing a 32-bit microcomputer for controlling devices has been developed for built-in applications in the fields of digital and network appliances.
In the following description, the microprocessor part of the LSI will be called “microcomputer core.”
FIG. 1 shows a chip layout of a cache in a one-chip LSI according to a first embodiment of the present invention;
FIG. 2 shows a chip layout of a cache in a one-chip LSI according to a second embodiment of the present invention;
FIG. 3 shows a chip layout of the cache according to the second embodiment;
Embodiments of the present invention will be described below with reference to FIGS. 1 to 4 and FIGS. 11 to 15.
In FIGS. 1 to 3 showing a layout of modules of the embodiments, the actual distance between blocks is negligible in calculating line lengths.
First Embodiment