Method and apparatus for an energy efficient operation of multiple processors in a memory

#This invention relates to computer structures, and in particular to a parallel processing memory chip containing single instruction, multiple data path processors.

#In conventional Von Neumann computer architectures, the speed of the processor is often restricted by the bandwidth of the interconnecting data bus, which is typically 8 to 64 bits in word width. In order to increase the speed of computers restricted by such constraints, parallel computer architectures have been designed, for example, those described briefly below.

#In a structure called The Connection Machine, 64K processors are used with 4K bits of memory allocated to each processor. The memory permits two read functions and a write function in one processor cycle to support three operand instructions. The connection Machine integrated circuit chip contains 16 processors and a hypercube routing node. A high performance interconnect network is a major feature of the architecture. The peak performance of the connection machine is about 1,000 MIPS, using a 32 bit addition function as a reference. A description of The Connection Machine may be found in Scientific American article “Trends in Computers”, by W. Daniel Hillis, Special Issue/Vol. 1, page 24ff.

#A better understanding of the invention will be understood with reference to the description below and to the attached drawings, in which:

#FIG. 1 is a block schematic of a typical prior art computer memory, and its connection to a central processing unit;

#FIG. 2 is a block schematic of the memory of the present invention, and its connection to a central processing unit;

#Turning to FIG. 1, a memory comprised of memory portions (chips) 1A and 1B is shown. A central processing unit 2 is connected to a cache memory 3, which is connected to refresh circuitry 4, which is connected to memory address and row decode circuitry 5A and 5B. The computer input/output (I/O) circuit 6 is connected to the address and data bus 7 which is connected to cache 3. Each of the representative memory portions 1A and 1B is comprised of row decode circuitry 5A, 5B, a memory cell array 8A, 8B, sense amplifiers 9A, 9B connected to each column of memory cells, and column decode circuitry 10A, 10B.

#In operation, CPU 2 addresses a row and column of a memory cell array in a well known manner, and applies a read enable or write enable signal to the decode circuitry which either reads or stores a bit in a memory cell via the sense amplifiers.

#A representative CMOS memory cell is illustrated in FIG. B11 of Microcomputer Primer by Mitchell Waite and Michael Pardee, Howard W. Sams & Co. Inc., Copyright 1976. While that storage cell is a six transistor storage cell, a single MOS storage element with capacitor storage cell is shown in FIG. B13. Descriptions of operation of the aforenoted storage cells are found on pages 204-207 of the aforenoted publication; such memory cells are well known to those skilled in the art and therefore will not be repeated here. The column, bit or data lines are commonly illustrated as vertical lines, to which the sense amplifiers are connected and the word or row lines are commonly shown as horizontal lines. Operation of read/write memories of various types is described in appendix B, page 199ff of the aforenoted publication, and need not be described further herein.