Conditional read and invalidate for use in coherent multiprocessor systems

#The present invention relates generally to coherent multiprocessor systems and, more particularly, to systems and techniques employed to maintain data coherency.

#Maintaining memory coherency among devices or agents (e.g., the individual processors) within a multiprocessor system is a crucial aspect of multiprocessor system design. Each of the agents within the coherency domain of a multiprocessor system typically maintains one or more private or internal caches that include one or more cache blocks or lines corresponding to portions of system memory. As a result, a cache coherency protocol is needed to control the conveyance of data between these internal caches and system memory. In general, cache coherency protocols prevent multiple caching agents from simultaneously modifying respective cache blocks or lines corresponding to the same system memory to have different or inconsistent data.

#Hardware-based cache coherency protocols are commonly used with multiprocessor systems. Hardware-based cache coherency protocols typically enable the cache controllers within the processors of a multiprocessor system to snoop or watch the communications occurring via an interconnection network (e.g., a shared bus) that communicatively links the processors. Additionally, hardware-based cache coherency protocols typically enable the cache controllers to establish one of a plurality of different cache states for each cache block associated with the processors or other caching agents. Three hardware-based cache coherency protocols are commonly known by the acronyms that represent the cache states which are possible under each of the protocols. Namely, MSI, MESI and MOESI, in which the letter “M” represents a modified state, the letter “S” represents a shared state, the letter “E” represents an exclusive state, the letter “O” represents an owned state and the letter “I” represents an invalid state.

#FIG. 1 is a block diagram of an example of a multiprocessor system;

#FIG. 2 is a flow diagram that depicts by way of an example one manner in which the processors within the multiprocessor system shown in FIG. 1 generate conditional read and invalidate requests;

#FIG. 3 is a flow diagram that depicts by way of an example one manner in which the processors within the multiprocessor system shown in FIG. 1 process conditional read and invalidate requests; and

#FIG. 1 is a block diagram of an example of a multiprocessor system 10. As shown in FIG. 1, the multiprocessor system 10 includes a plurality of processors 12 and 14 that are communicatively coupled via an interconnection network 16. The processors 12 and 14 are implemented using any desired processing unit such as, for example, Intel Pentium™ processors, Intel Itanium™ processors and/or Intel Xscale™ processors.

#The interconnection network 16 is implemented using any suitable shared bus or other communication network or interface that permits multiple processors to communicate with each other and, if desired, with other system agents such as, for example, memory controllers. Further, while the interconnection network 16 is preferably implemented using a hardwired communication medium, other communication media, including wireless media, could be used instead.

#As depicted in FIG. 1, the multiprocessor system 10 also includes a system memory 18 communicatively coupled to a memory controller 20, which is communicatively coupled to the processors 12 and 14 via the interconnection network 16. Additionally, the processors 12 and 14 respectively include caches 22 and 24, cache controllers 26 and 28 and request queues 30 and 32.