Sparse-coefficient functions for reducing computational requirements
AssigneeVisteon Global Technologies, Inc.
InventorsJ. William Whikehart, Christopher John Hagan
Life of this patent
Estimating the term…
Loading patent…
AssigneeVisteon Global Technologies, Inc.
InventorsJ. William Whikehart, Christopher John Hagan
Estimating the term…
A method for reducing computational steps in a digital processor including multiplications producing a plurality of multiplication products. This method specifies a desired multiplication function to be implemented in a digital processor, the desired multiplication function having a respective set of initial coefficients corresponding to each digital multiplier stage of the multiplication function. An initial total number of non-zero bits of the initial coefficients is determined and the initial coefficients are modified. Further, a resulting number of non-zero bits in the modified set of coefficients is quantified. Finally, the modified set of coefficients that result in a reduced number of non-zero bits as compared to the initial coefficients is chosen. The new modified coefficients are implemented in the device by constructing the digital multiplier stages with the modified coefficients. Thus, the digital processor performs a desired multiplication function using “sparse” coefficients to achieve a reduced execution time or lower implementation cost for a given signal conditioning function.
A method for reducing computational steps in a digital processor having multiplication operations that produce a plurality of multiplication products, wherein the multiplication operations are used to carry out a desired signal processing function, said method comprising:
A method for reducing computational steps in a digital processor including digital multiplication operations that produce a plurality of multiplication products, wherein the multiplication operations are used to carry out a desired signal processing function, said method comprising:
A method for reducing computational steps in a digital processor including shift-and-add digital multiplier stages producing a multiplication product, said method comprising:
Dependencies are inferred from the claim text.