Arithmetic processing unit and semiconductor device

An arithmetic processing unit comprising:

• instruction storage means in which an instruction for directing a predetermined arithmetic operation is stored;
• data storage means in which a plurality of floating point numbers are stored;
• interval specifying means adapted to retrieve the instruction from said instruction storage means and retrieve two or more floating point numbers from said data storage means according to the instruction and specify an upper bound and a lower bound between which an exact value lies for each of the retrieved two or more floating point numbers;
• arithmetic operation means adapted to retrieve the instruction from said instruction storage means and retrieve two or more upper bounds and two or more lower bounds that are specified by said interval specifying means according to the instruction, said arithmetic operation means being for performing the predetermined arithmetic operation designated by the retrieved predetermined instruction, using the retrieved two or more upper bounds and the retrieved two or more lower bounds;
• and
• operation result selecting means for selecting an operation result that satisfies a predetermined condition from the operation results obtained as a result of operations by said arithmetic operation means to write the selected operation result in said data storage means,
• said instruction storage means, said data storage means, said interval specifying means, and said arithmetic operation means being achieved by hardware implementations.

An arithmetic processing unit comprising:

• data storage means in which a plurality of numerical values with errors are stored;
• interval specifying means adapted to retrieve two or more numerical values with errors from said data storage means to specify an upper bound and a lower bound between which errors lie for each of the retrieved two or more numerical values with errors;
• and
• arithmetic operation means for performing a predetermined arithmetic operation using the upper bound and the lower bound for each of two or more numerical values with errors that are specified by said interval specifying means,
• said data storage means, said interval specifying means, and said arithmetic operation means being achieved by hardware implementations.

A semiconductor device comprising:

• an instruction memory in which an instruction for directing a predetermined arithmetic operation is stored;
• a data memory in which a plurality of floating point numbers are stored;
• an interval specifying section adapted to retrieve the instruction from said instruction memory and retrieve two or more floating point numbers from said data memory according to the instruction and specify an upper bound and a lower bound between which an exact value lies for each of the retrieved two or more floating point numbers;
• arithmetic operation section adapted to retrieve the instruction from said instruction memory and retrieve two or more upper bounds and two or more lower bounds that are specified by said interval specifying section according to the instruction, said arithmetic operation section being for performing the predetermined arithmetic operation designated by the retrieved predetermined instruction, using the retrieved two or more upper bounds and the retrieved two or more lower bounds;
• and
• operation result selecting section for selecting an operation result with the highest value and an operation result with the lowest value, from the operation results obtained as a result of operations by said arithmetic operation section to write the selected operation result in said data memory.