Compensation scheme for reducing delay in a digital impedance matching circuit to improve return loss
AssigneeTexas Instruments Incorporated
InventorsWing K. Chan, Joseph T. Nabicht
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AssigneeTexas Instruments Incorporated
InventorsWing K. Chan, Joseph T. Nabicht
Estimating the term…
A simple, power efficient and inexpensive digital compensation scheme for reducing delay in a digital impedance matching circuit to improve return loss. The scheme employs a digital filter to compensate for the absolute sampling and digital delays associated with a digital impedance matching circuit. The digital filter is based on the low-pass function of a DAC response, and can easily be modified to correct for not only the DAC response delay, but also other delays in the digital impedance matching circuit. The digital filter is very simple to implement and can add or subtract delays from the overall system.
A digital impedance matching circuit delay compensation system comprising:
A phase delay compensation system comprising:
A method of compensating a digital impedance matching circuit to improve return loss comprising the steps of:
Dependencies are inferred from the claim text.
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1. Field of the Invention
This invention relates generally to impedance matching circuits, and more particularly, to a digital compensation scheme for reducing delay in a digital impedance matching circuit to improve return loss.
2. Description of the Prior Art
Other aspects, features and advantages of the present invention will be readily appreciated, as the invention becomes better understood by reference to the following detailed description, when considered in connection with the accompanying drawing figures wherein:
FIG. 1 illustrates amplitude and phase response plots for a DAC low pass filter;
FIG. 2 illustrates amplitude and phase response plots for an inverse DAC low pass filter;
While the above-identified drawing figures set forth particular embodiments, other embodiments of the present invention are also contemplated, as noted in the discussion. In all cases, this disclosure presents illustrated embodiments of the present invention by way of representation and not limitation. Numerous other modifications and embodiments can be devised by those skilled in the art which fall within the scope and spirit of the principles of this invention.
The embodiments described herein below are directed to techniques including structures and methods for correcting the phase delay through a digital impedance matching system. These techniques allow digital circuits to synthesize a more accurate matching impedance to improve return loss. It will also be shown that the return loss of a system is dependent on both the amplitude matching and also the delay in the system. Even if the amplitude of the return signal is matched correctly to the incident signal therefore, a significant delay in the signal will cause a significant degradation in the return loss.
The return loss can be affected by a phase difference between the incident and reflected voltages, which translates to reactive differences in the line impedance and the matching impedance. For a given return loss then, there will be a specific phase difference. The amplitude variation and the phase variation must be kept to a minimum on all components to ensure an effective impedance matching circuit. The amplitude variation is fairly easy to control with gain and filter settings. Digital processing of the input signal to synthesize a matching impedance however, requires some finite amount of time. This delay in time or phase angle will result in an amplitude mismatch that translates directly into a worse return loss number. One way to lessen the phase difference is to correct for any phase delay caused by sampling and digital filters.
Networks using digital techniques: impedance matching networks
Impedance networks
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