Low power vector summation method and apparatus
AssigneeAgere Systems Inc.
InventorsKameran Azadet, Meng-Lin Yu, Zhan Yu
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Abstract
An arrangement is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.
Claims17
A method for operating an arithmetic processor comprising the steps of:
- causing at least one coefficient of the arithmetic processor to be implemented in 2's complement reduced representation arithmetic;
- and
- adding a compensation vector for the at least one coefficient at an end of an accumulation path for the arithmetic processor.
An arithmetic processing circuit having a plurality of taps comprising:
- a partial product generator operative to generate a partial product in 2's complement reduced representation;
- and
- logic means operating on bit positions of the partial product generator for detecting a sign bit thereof and causing the complementation of the sign bit.
A coefficient magnitude detector comprising:
- a plurality of XNOR gates for detecting a start of sign extension bits for a given coefficient;
- a plurality of AND gates for detecting start of sign extension positions of all coefficients in an identified grouping of coefficient taps;
- and
- a leading zero detector for detecting the sign extension position at a highest MSB bit position within the identified grouping of coefficient taps.
Dependencies are inferred from the claim text.