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AssigneeSun Microsystems, Inc.
InventorsPradiptya Ghosh, Robert J. Walsh, Tuan V. Doan, Jean Hassoun
Estimating the term…
Data clusters are added between functional blocks in a higher-level hierarchical circuit model. The data clusters account for inter-level parasitic values without flattening the circuit model to a lower hierarchical level and operate as an information graph or network between nodes, which can be used with the standard, or default, information graph between nodes. The data clusters also allow the use of standard functional blocks without introducing artificial nodes into the circuit at a lower level that could create a coupling point at a higher level. The use of data clusters allows rapid and accurate modeling of the circuit without flattening the circuit to the lowest level.
A cluster graph stored in a computer-readable medium for use in a simulation of an integrated circuit on a computer-aided-design (“CAD”) tool, the cluster graph comprising:
The cluster graph of claim I wherein the data representing inter-level coupling of the integrated circuit comprises a resistor-capacitor tree.
A cluster graph stored in a computer-readable medium for use in a simulation of an integrated circuit on a computer-aided-design (“CAD”) tool, the cluster graph comprising:
An integrated electronic circuit model stored on a computer-readable medium, the integrated electronic circuit model comprising:
An integrated electronic circuit model stored on a computer-readable medium, the integrated electronic circuit model comprising:
A method of creating an inter-level cluster graph for simulating inter-level coupling in an hierarchical integrated electronic circuit model on a computer-aided-design (“CAD”) tool, the method comprising:
A method of modeling an integrated circuit on a computer system, the method comprising:
Dependencies are inferred from the claim text.
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Circuit design at the analogue level: design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE],…
Computing and data processing
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FIG. 1 is a simplified diagram illustrating a hierarchical data structure.
FIG. 2A is a simplified circuit diagram of a block at one level of hierarchy with gates at a lower level of hierarchy.
FIG. 2B is a simplified diagram representing the gate shown in FIG. 2A.
Cluster graphs containing inter-leveling coupling data are overlayed with bases cluster in a hierarchical model of an electronic circuit on a CAD tool. This relieves the circuit designer from modifying a standard object in the library or having to flatten the data model to the transistor level. This shortens run time and provides a flexible, accurate, and convenient way for the circuit designer to evaluate inter-hierarchy coupling effects without propagating virtual nodes.
FIG. 1 is a simplified diagram of a hierarchy 10 that might be used in a CAD environment. The descriptions of the levels of hierarchy are exemplary only, and other levels might be defined in another CAD environment, or levels might be combined or omitted, depending on the type of CAD tool being used and the circuit being designed.
If an electronic circuit that is to be fabricated on a chip is the design goal, the top-level hierarchy 12 might relate to the flow plan of the chip. The second level hierarchy 14 might relate to the block level, where specific functional blocks are defined to achieve the flow plan of the higher level. Some blocks might be very specific in order to implement the higher-level hierarchy. The third level hierarchy 16 might relate to sub-blocks that combine various data paths and control blocks into commonly used elements of this level of hierarchy. Commonly used elements might be data processing routines, for example, that are used in several of the blocks of the higher-level hierarchy.