Method of estimating a lifetime of hot carrier of MOS transistor, and simulation of hot carrier degradation

#The present invention relates to a method of estimating a lifetime concerning hot carrier degradation of a MOS transistor. More specifically, it relates to improvement of accuracy in lifetime estimation in a case of applying a substrate voltage. The present invention also relates to a method of simulating circuit characteristic degradation caused by hot carrier degradation of a MOS transistor. More specifically, it relates to improvement of simulation in a case of applying a substrate voltage.

#The size of MOS transistors has been reduced considerably with a trend toward high density, high integration and miniaturization of semiconductor integrated circuit devices. With the miniaturization trend, especially due to the decreasing channel length, hot carrier degradation has been a critical problem, since the degradation will affect the reliability of a MOS transistor. Hot carrier degradation refers to a phenomenon in which highly energized electrons and positive holes (hereinafter ‘hot carrier’) are generated by a high electric field at a drain end of a MOS transistor, which will degrade the characteristics of a gate oxide film. This hot carrier degradation includes plural degradation modes. In degradation under a condition to cause a maximum substrate current or degradation under a condition that the gate voltage Vgs is a half the drain voltage Vds, a drain current is decreased over time for both N-type and P-type MOS transistors. As a result, the delay time of the circuit is increased over time. When the delay reaches a certain degree, a timing error occurs at a time of input/output of signals within the semiconductor integral circuit or between the circuit and outside, and this causes a malfunction of an entire system in which the semiconductor integrated circuit is assembled.

#Regarding the hot carrier degradation, hot carrier reliability has been evaluated by a stress acceleration experiment under a DC (direct current) condition with respect to the MOS transistor. Product reliability has been provided by optimizing a production process to satisfy the hot carrier evaluation standard.

#FIG. 1 is an explanatory view to show a method of estimating a lifetime on the basis of a hot carrier lifetime model in an embodiment of the present invention.

#FIG. 2 is an explanatory view to show a method of extracting a hot carrier lifetime parameter as a constant in an embodiment of the present invention.

#FIG. 3 is an explanatory view to show a method of extracting a hot carrier lifetime parameter as a constant in an embodiment of the present invention.

#Embodiments according to the present invention are further explained below by referring to the drawings.

#FIG. 1 shows a method of estimating a lifetime based on hot carrier lifetime model formulas (12), (13) and (14) according to the present invention. In FIG. 1, the vertical axis is a logarithmic scale of a value τ·(Id/W)2 calculated from a lifetime τ in a DC stress experiment, a drain current Id during a stress, and a gate width W of a MOS transistor. The horizontal axis is a logarithmic scale of a ratio Isub/Id, where Isub is a substrate current during a stress and Id is a drain current. Data indicated with respective marks of ∘, x, □, ⋄, Δ are values measured under varied conditions. Here, Vgs@Isubmax denotes a gate-source voltage Vgs at the time that the substrate current Isub becomes maximum. The plural curves denote fitting curves based on the hot carrier model formulas (12), (13) and (14) corresponding to the respective substrate voltages. A point 1 on the horizontal axis denotes a maximum value of Isub/Id in actual use, and a point 2 on the vertical axis denotes a value of τ·(Id/W)2 on the fitting curves at the maximum value of the substrate voltage and Isub/Id in actual use.

#As shown in FIG. 1, the hot carrier lifetime deteriorates with application of substrate voltage. According to this model, based on physical grounds, deterioration of this hot carrier lifetime caused by application of substrate voltage can be written accurately with respect to wide ranges of drain and gate voltages. An estimated lifetime at the maximum values of the substrate voltage and Isub/Id in actual use can be calculated on the basis of a value τ·(Id/W)2 determined at the point 2 on the τ·(Id/W)2 axis.