Automatic test vector generation method, test method making use of the test vectors as automatically generated, chip manufacturing method and automatic test vector generation program

#This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-375860, filed Dec. 28, 1999; the entire contents of which are incorporated herein by reference.

#1.Field of the Invention

#The present invention is related to a test vector generation method and a program for automatically generating test vectors for use in testing whether or not instructions are implemented in a processor in agreement with the predetermined specifications of the instruction set architecture (ISA), and a test method and a chip manufacturing method making use of the test vectors as generated by the test vector generation method.

#FIG. 1 is a flowchart showing the procedure in accordance with a method of automatically generating test vectors of the present invention.

#FIG. 2 is a block diagram showing an automatic test vector generating system in accordance with a first embodiment.

#FIG. 3 is a flowchart showing the procedure in accordance with the method of automatically generating test vectors of the first embodiment.

#In the following description, several embodiments of the present invention will be explained.

#FIG. 1 is a flowchart showing the procedure in accordance with a method of automatically generating test vectors of the present invention. As illustrated in the same figure, in accordance with the present invention, the instruction set architecture (ISA) of a processor as given is analyzed in the step S101; the data required for generating test vectors are generated in the step S103 on the basis of the result of the analysis; and test vectors are generated in the step S105 on the basis of the data as generated. The function of the processor are then tested by running a simulation program with the test vectors as generated in an EWS(Engineering Work Station) in order to simulate the function of the processor under the test in the step S106; the design of the processor is logic synthesized in the step S107 after confirming the function; the circuit layout of the processor is generated by the use of the result of the logic synthesis in the step S108; masks are generated by the use of the circuit layout as generated in the step S109; and finally wafers are produced by the use of the masks as generated in the step S110.

#The ISA specifications include specifications of addition instructions, branch instructions and so forth.