Wireless data communications using FIFO for synchronization memory
AssigneeBroadcom Corporation
InventorsSherman Lee, Vivian Y. Chou, John H. Lin
Life of this patent
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AssigneeBroadcom Corporation
InventorsSherman Lee, Vivian Y. Chou, John H. Lin
Estimating the term…
A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched or updated RAM microcode is utilized or executed only to the extent of changes to the ROM microcode, otherwise the ROM microcode is executed in its normal fashion. When a patch is received, it is loaded into system RAM along with instructions or other appropriate signals to direct the execution of the patched or updated microcode from RAM instead of the existing ROM microcode. Various methods are presented for selecting the execution of the appropriate microcode depending upon whether there have been changes made to it.
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A memory management method comprising:
A system comprising:
A system comprising:
A system comprising:
A system comprising:
A memory management method comprising:
Dependencies are inferred from the claim text.
From the US filing history. Foreign family members aren’t listed.
Backward citations are indexed for grants only.
For non-sequential address: for runtime instruction patching
Updates: of program code stored in read-only memory [ROM]
Arrangements for next microinstruction selection: microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle…
Using frequency hopping: arrangements for sequence synchronisation
Term end not estimated
1. Field of the Invention
This invention relates to wireless communication and more particularly to an apparatus that receives transmission of data synchronized to a clock that is out of phase with the clock of the apparatus.
This invention also relates to microprocessor system architecture, and more particularly to a microprocessor architecture that allows read-only memory (ROM) microcode to be effectively altered or enhanced without the need to reprogram or replace the ROM.
FIG. 1 illustrates, in a block diagram, a wireless network involving wireless devices.
FIG. 2A illustrates, in a block diagram, a wireless device of FIG. 1 in accordance with one embodiment of the invention.
FIG. 2B illustrates, in a block diagram, a radio frequency (RF) receiver of FIG. 2A.
A wireless network 100 (FIG. 1) includes a plurality of wireless devices 102-1, 102-2 . . . 102-i . . . 102-n (2≦i≦n). Wireless network 100 includes radio frequency (RF) networks, optical networks, and infrared networks. Wireless network 100 is, for example, a Bluetooth piconet where wireless device 102-1 is a master Bluetooth radio and wireless devices 102-2 to 102-n are slave Bluetooth radios. As one skilled in the art understands, a Bluetooth piconet can form part of a larger Bluetooth scatternet.
In accordance with one aspect of the invention hereafter referred to as “thin baseband/host-based”, wireless device 102-i (FIG. 2A) performs radio and baseband modulation functions in circuitry. A host 220 performs all other baseband, link management, and protocol stack functions through software. Host 220 includes a high performance and low latency host processor (e.g., reduced instruction-set computing processors) capable of handling time-critical link management functions. Such processors are available from ARM Ltd. of Cambridge, England, MIPS Technologies, Inc. of Mountain View, ARC Cores, Inc. of San Jose, and Tensillica of Santa Clara.
Wireless device 102-i includes in one embodiment a conventional radio frequency (RF) receiver 202 (FIG. 2A) that receives RF signals from another Bluetooth radio via an antenna 204. The RF signals carry data synchronized to the clock (“external clock”) of the another Bluetooth radio. RF receiver 202 decodes the RF signals to recover the data signals and the external clock signals (symbol timing recovery). RF receiver 202 respectively outputs the data signals and the external clock signals via respective lines 206 and 208.