Dual mode class D amplifiers

#The present invention relates generally to class D amplifiers and, more particularly, to class D amplifiers that have one or more modes of operation for avoiding AM radio harmonic frequencies during operation.

#Class D power amplifiers are typically pulse-width modulated amplifiers that switch at frequencies well above the top of the audio band, often at frequencies of 100 kHz or greater. When a class D amplifier switches at these high frequencies, the switching frequency or its harmonics can interfere with AM radio receivers that are located close to the class D amplifier. Because of these interference problems, class D amplifiers cannot be easily integrated into consumer electronic products, such as stereo receivers, that have an AM tuner and power amplifier in the same chassis. Class D modulators switching in the 50 khz to 2 MHz range generate harmonics which interfere with AM radio reception. This has precluded wide spread acceptance of class D in products with an AM radio.

#The AM radio broadcast band spans from 540 to 1700 kHz in the US and up to 30 MHz worldwide. To sample a 20 khz audio signal, class D modulators must run at frequencies greater than 200 khz. Because the output of these modulators is a pulse width modulated square wave, the modulators generate both even and odd harmonics. The low pass filter that removes the carrier from the speaker leads also attenuates these harmonics. However, it is not practical to design a filter with adequate high frequency attenuation and still pass 20 kHz audio signals without interfering with the sensitive AM receiver bandpass. Furthermore, the printed circuit board traces carrying the pulse width modulated square wave tend to radiate radio frequency energy that may be picked up by the AM antenna.

#FIG. 1 is a schematic of a typical prior art class D amplifier;

#FIG. 2 is a schematic diagram of a dual mode harmonic avoidance class D amplifier;

#FIG. 3 is a schematic diagram of a dual mode combined class D/AB amplifier;

#Advances in MOSFET technology as well as advances in integrated circuits have made it possible to apply class D amplifiers to audio applications. Class D amplifiers are significantly more efficient than class AB amplifiers. In the past, disadvantages of class D amplifiers included higher parts count, cost, electromagnetic interference, and poor performance. With increased integration and the introduction of sophisticated control integrated circuits these disadvantages are becoming less pronounced. In the near future, class D amplifiers will replace class AB amplifiers in many applications. Class D amplifiers already have a clear advantage in high power applications. As the cost and component count of these amplifiers fall, class D amplifiers will be able to complete with class AB amplifiers in low and medium power applications.

#To overcome the poor performance of class D amplifiers, others have suggested a self oscillating variable frequency modulator as shown in FIG. 1. An integrator 10 has an audio input over an input resistor RIN. It has a digital feedback input A over resistor RDFB, and an analog feedback at input B over resistor RAFB. The respective analog and digital feedback signals A, B, are taken from the output of the bridge circuit 20 and the low-pass filter that comprises the inductor L and capacitor CLP. For purposes of understanding, let us simply focus on the digital output A and assume that there is no audio input. In this case, the output at point A is a square wave with a 50% duty cycle. When the square wave is high, current flows through RDFB into the summing junction of the integrator 10. Its output ramps down until it reaches the negative threshold of the comparator 12. R1 and R2 are used to add hysteresis to the comparator 12. These resistors can be used to adjust the comparator positive and negative thresholds. When the output of the comparator 12 goes low, the upper FET 22 turns off and after a short delay the lower FET 24 turns on. The square wave goes low, and current now flows out of the integrator 10 summing junction through RDFB. The output of the integrator 10 reverses and ramps up until it reaches the positive threshold of the comparator 12. This signals the lower FET 24 to turn off and after a short delay the upper FET 22 turns on. The square wave goes high and the cycle continues. With no audio signal, the output at A is a 50% square wave, and the output of the integrator 10 is a triangle wave.

#Now consider the case when an audio signal is applied. Assuming that the audio signal is positive, then current flows through RIN into the integrator summing junction. Current also flows through RAFB out of the summing junction (negative feedback). The net contribution of the audio signal to the integrator summing junction current is IRIN−IRAFB. When the upper FET 22 is on, the currents IDFB and (IRIN−IRAFB) are both into the summing junction. This speeds up the ramp at the output of the integrator 10. When the lower FET 24 is on, the current through IDFB reverses and the two current now are in opposite directions. This slows the ramp down. A similar analysis can be applied to the case where the input signal is negative.