Methods, apparatus and slurries for chemical mechanical planarization

#The present invention concerns methods and apparatus for the chemical-mechanical planarization of articles such as semiconductor wafers.

#Current trends in the integrated circuit (IC) industry include fabricating smaller devices having increased chip density. Reducing chip size can reduce chip manufacturing costs. In addition, devices having smaller dimensions can be advantageous because device delay can also be decreased, thereby increasing performance.

#In addition, device performance can be increased by adding multiple levels of metallization. The use of multiple levels of metal interconnections allows for wider interconnect layer dimensions with shorter interconnect lengths. Because such lengths have only been possible with single level devices, a corresponding decrease in interconnect delay has been achieved. Nonetheless, as many interconnect levels are added, topography that builds up with each level can become severe. If not resolved, these topographies can adversely affect the reliability of the device.

#FIG. 1 is a schematic illustration of an apparatus of the present invention, with the planarization steps being carried out with a rotating pad within a pressure vessel;

#FIG. 2 is a schematic illustration of an alternative embodiment of an apparatus of the present invention, with the planarization steps being carried out with a linear continuous belt within a pressure vessel;

#FIG. 3 is a schematic illustration of a CMP system according to the present invention;

#The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.

#In general, the invention can be used for the fabrication of articles such as integrated circuits (ICs), including, for example, memory ICs such as random access memories (RAMs), dynamic random access memories (DRAMs), or synchronous DRAMs (SDRAMs). The ICs may also include other types of circuits such as application specific ICs (ASICs), merged DRAM-logic circuits (embedded DRAMs), other logic circuits, etc.

#The invention may be used to provide CMP of or for, inter alia, deep trench capacitor fabrication, shallow trench isolation, polysilicon films, photoresists and superconducting circuits. The CMP of the present invention may be used for planarizing Al, Al alloys, polymers, inlaid metal, diffusion barriers and adhesion promoters. The present invention may also be used to planarize both the dielectric layers and metal layers/plugs/lines in a damascene or dual damascene process. In particular, the CMP of the present invention may be employed to form IC's with copper interconnects using a damascene or dual damascene process.