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US 2003/0194952 A1Published application
Method for planarizing a dielectric layer of a flash memory device
AssigneeMacronix International Co., Ltd.
InventorChi-Tung Huang
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AssigneeMacronix International Co., Ltd.
InventorChi-Tung Huang
Estimating the term…
A method for planarizing the dielectric layer of a flash memory device, wherein the method is applied on substrate of a flash memory device having a plurality of gate structures formed thereon and a protective layer is formed on the gate structures. A dielectric layer is formed on the substrate, filling the space between the gate structures and covering the protective layer. Using the protective layer as a polishing endpoint layer, a fixed base and a polishing slurry that does not contain metal ions are used to chemical mechanically polish and to planarize the dielectric layer. The fixed base includes a base and evenly distributed polishing abrasives fixed onto the base.
A method for planarizing a dielectric layer of a flash memory device, comprising:
A planarizing method for a dielectric layer of a memory device, comprising:
Dependencies are inferred from the claim text.
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Erasable-and-programmable rom [eprom] devices not provided for in groups h10b41/00 - h10b63/00
Operating processes therefor: characterised by the composition of the lapping agent
Characterised by the composition or properties of the pad materials: pads with fixed abrasives
Lapping pads for working plane surfaces: characterised by the shape of the lapping pad surface, e.g. grooved
Term end not estimated
1. Field of Invention
This invention relates to a method for planarizing a semiconductor device. More particularly, the present invention relates to a method for planarizing the dielectric layer of a flash memory device.
2. Description of Related Art
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,
FIGS. 1A through 1F are schematic, cross-sectional views, illustrating the successive steps in polishing the dielectric layer of a flash memory device according to the prior art.
FIGS. 2A through 2E are schematic, cross-sectional views, illustrating the successive steps for planarizing the dielectric layer of a flash memory device according to a preferred embodiment of the present invention.
FIGS. 2A through 2E are schematic, cross-sectional views, illustrating successive steps for planarizing the dielectric layer of a flash memory device according to a preferred embodiment of the present invention. Furthermore, the present invention is applicable to the Mask Read-Only Memory (Mask ROM) or the Electrically-Erasable-Programmable-Read-Only Memory (E2PROM).
Referring to FIG. 2A, a substrate 200, wherein gate structures 202 already formed thereon, is provided. A protective layer 204 is formed on the gate structures 202. The gate structure 202 of a flash memory is formed with, for example, polysilicon.
As shown in FIG. 2B, a dielectric layer 206 with good step coverage and gap filling properties is formed on the substrate 200, filling the space between the gate structures 202 and covering the protective layer 204. The dielectric layer 206 is, for example, a high density plasma (HDP) oxide layer, a plasma enhanced (PE) oxide layer, a tetraethylorthosilicate (TEOS) oxide layer or a silicon oxynitride (SiON) layer.