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AssigneeMacronix International Co., Ltd.
InventorShu-Ya Hsu
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A method for forming a sidewall oxide layer of a shallow trench isolation with reduced stress and encroachment is disclosed. The method utilizes introductions of oxygen and hydroxyl to perform an in situ steam generated process to form a sidewall oxide layer in a shallow trench isolation. The sidewall oxide layer formed by the method of this invention has less stress and the processing time is also much shorter than the processing time of the conventional thermal oxidation processes.
A method for forming a sidewall oxide layer of a shallow trench isolation, said method comprising:
A method for forming a sidewall oxide layer of a shallow trench isolation, said method comprising:
A method for forming a sidewall oxide layer of a shallow trench isolation, said method comprising:
Dependencies are inferred from the claim text.
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Of Group IV semiconductors: of silicon in uncombined form, i.e. pure silicon
Non-deposition formation processes: formation by thermal treatments
Of isolation regions comprising dielectric materials: using trench refilling with dielectric materials, e.g. shallow trench isolations
Isolation regions comprising dielectric materials: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
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1. Field of the Invention
The present invention relates to a method for forming a sidewall oxide layer of a shallow trench isolation, and more particularly to a method for forming a sidewall oxide layer of a shallow trench isolation with reduced stress and encroachment.
2. Description of the Related Art
The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
FIG. 1 shows a cross-sectional diagram of a shallow trench isolation amid a STI conventional process;
FIG. 2A shows two dielectric layers sequentially formed over a substrate;
It is to be understood and appreciated that the process steps and structures described below do not cover a complete process flow. The present invention can be practiced in conjunction with various integrated circuit fabrication techniques that are used in the art, and only so much of the commonly practiced process steps are included herein as are necessary to provide an understanding of the present invention.
The present invention will be described in detail with reference to the accompanying drawings. It should be noted that the drawings are in greatly simplified form and they are not drawn to scale. Moreover, dimensions have been exaggerated in order to provide a clear illustration and understanding of the present invention.
Referring to FIG. 2A, dielectric layers 202 and 204 are sequentially formed over a substrate 200. The substrate 200 preferably comprises, but is not limited to: a silicon substrate with a <100> crystallographic orientation. The substrate can also comprise other semiconductor substrate such as a SOI (Silicon On Insulator)substrate. The dielectric layer 202 preferably comprises, but is not limited to: a silicon dioxide layer formed by a thermal growth process. The dielectric layer 202 can be a silicon oxy-nitride layer. The dielectric layer 202 has a thickness of from about 20 angstrom to about 300 angstrom. The dielectric layer 204 preferably comprises a silicon nitride layer formed by conventional methods such as chemical vapor deposition, but other material met the spirit of this invention should not be excluded. The dielectric layer 204 can also be a silicon oxy-nitride layer. The silicon nitride layer 204 preferably has a thickness of from about 100 angstrom to about 2000 angstrom.