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US 2003/0194865 A1Published application
Method of manufacture of programmable conductor memory
AssigneeMicron Technology, Inc.
InventorTerry L. Gilton
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AssigneeMicron Technology, Inc.
InventorTerry L. Gilton
Estimating the term…
Programmable conductor memory cells in a stud configuration are fabricated in an integrated circuit by blanket deposition of layers. The layers include a bottom electrode in contact with a conductive region in a semiconductor substrate, a glass electrolyte layer that forms the body of the cell and a top electrode layer. Under the influence of an applied voltage, conductive paths grow through or along the cell body. The layers are patterned and etched to define separate pillars or cells of these stacked materials. A liner layer of an insulating material is deposited over the cells and acts as a barrier to prevent diffusion of the metal in the cell body into other parts of the integrated circuit. Remaining regions between the cells are filled with an insulating layer. At least some of the insulating layer and some of the liner layer are removed to make contact to the top electrode layer of the cell and to the substrate.
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A method of fabricating switching devices for integrated circuits, comprising:
A method of fabricating programmable conductor memory cells on a substrate by blanket layer deposition, comprising:
An array of programmable conductor memories in an integrated circuit comprising pillars of stacked materials on a semiconductor substrate.
A method of fabricating programmable conductor memory cells by blanket layer deposition and post-patterning, comprising:
Dependencies are inferred from the claim text.
From the US filing history. Foreign family members aren’t listed.
Backward citations are indexed for grants only.
RRAM elements whose operation depends upon chemical change: comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
Resistance change memory devices, e.g. resistive RAM [ReRAM] devices: arrangements comprising multiple bistable or multi-stable switching…
Modification of switching materials after formation, e.g. doping: by diffusion, e.g. photo-dissolution
Shaping switching materials: by etching of pre-deposited switching material layers, e.g. lithography
Term end not estimated
1. Field of the Invention
This invention relates generally to a method of manufacture of memory devices for integrated circuits and more particularly to programmable conductor memory arrays comprising glass electrolyte elements.
2. Description of the Related Art
These and other aspects of the invention will be better understood in view of the detailed description below and the appended drawings, which are meant to illustrate and not to limit the invention, and in which:
FIG. 1 is a schematic cross-section of a partially fabricated integrated circuit, showing blanket layers deposited on a semiconductor substrate according to a preferred embodiment of the present invention.
FIG. 2 is a schematic cross-section of the structure of FIG. 1 after patterning to define a programmable memory cell in a stud configuration.
The preferred embodiment discloses a method of fabricating a programmable memory cell in a stud configuration. Blanket layers of electrode and body materials are deposited and subsequently patterned and etched, leaving pillars or studs as individual devices. The blanket deposition of the layers avoids problems associated with via filling and allows more flexibility in cell configuration.
With reference to FIG. 1, a cross section of deposited blanket layers is shown. A semiconductor base material 100 containing a heavily doped (e.g., n+) conductive region 102 comprises the substrate 101 upon which the memory cells are fabricated. In general, the substrate comprises the lowest layer of semiconductor material from which devices are formed in the integrated circuit. In the illustrated embodiments, the substrate comprises a single-crystal silicon wafer. In other arrangements, an epitaxial silicon layer or another semiconductor, such as a III-V material, can be used.
A bottom electrode 103 makes contact with the substrate. The bottom electrode 103 can include more than one layer. In the illustrated embodiment the bottom electrode 103 comprises a layer of polysilicon 104, a layer of tungsten nitride 106 and a layer of tungsten 108. Preferably, the polysilicon layer 104 is between about 25 nm and 75 nm thick, the tungsten nitride layer 106 is between about 5 nm and 40 nm thick and the tungsten layer 108 is between about 50 nm and 100 nm thick.