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AssigneeApplied Materials, Inc.
InventorsPeijun Ding, Imran Hashim, Barry Chin, Bingxi Sun
Estimating the term…
A method and apparatus for Metallization process sequences are provided for forming reliable interconnects including lines, vias and contacts. An initial barrier layer, such as Ta or TaN, is first formed on a patterned substrate followed by seed layer formed using high density plasma PVD techniques. The structure is then filled using either 1) electroplating, 2) PVD reflow, 3) CVD followed by PVD reflow, or 4) CVD.
A process for forming an interconnect on a patterned substrate, comprising:
A process for forming an interconnect, comprising:
An integrated system for processing a substrate comprising:
Dependencies are inferred from the claim text.
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The barrier, adhesion or liner layers being seed or nucleation layers: for deposition from the gaseous phase, e.g. for chemical vapour deposition…
Characterised by the coating material: nitrides
On metallic substrates or on substrates of boron or silicon: by cathodic sputtering
Of conductive barrier, adhesion or liner layers: in openings in dielectrics
Term end not estimated
1. Field of the Invention
Embodiments of the present invention generally relate to an integrated circuit and flat panel display fabrication. More specifically, the invention relates to process sequences for fabricating copper interconnect structures and other metallization structures.
2. Background of the Related Art
So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
FIG. 1 is a flow diagram of the process sequences of the invention.
The invention is described below with reference to the flow diagram depicted in FIG. 1. Each of the process sequences begin with substrate preparation followed by a barrier layer deposition step. Several metal deposition sequences are then performed to complete the formation of the conductive interconnects.
The preferred embodiments described below can be carried out using process equipment available from Applied Materials, Inc., located in Santa Clara, Calif. The equipment includes an integrated Endura platform having a Preclean II chamber, an IMP PVD Ta/TaN chamber, a PVD Cu chamber, an IMP PVD Cu chamber, and a CVD Cu chamber. Electroplating can be performed using a commercially available system from Semitool, Inc., of Kalispell, Mont., or other electroplating equipment supplier.
FIG. 1 is a flow diagram showing the initial steps of each process of the invention. The processes of the invention are preferably performed on a substrate having one or more features such as contacts, vias, lines or other interconnect features formed thereon. The interconnect features may be any size and have any aspect ratio, however, the trend has been to decrease feature dimensions and increase aspect ratios. The invention has particular application in the small dimension (e.g., less than 0.25 μm), high aspect ratio (e.g., 3 or higher) features. The substrate is first preferably subjected to a cleaning process such as argon bombardment in a precleaning chamber where about 100 to about 300 Å of material on the substrate surface is removed to eliminate native oxides or other contaminants from the surface.