Method of manufacturing semiconductor device package
AssigneeSamsung Electro-Mechanics Co., Ltd.
InventorsChan Wang Park, Joon Ho Yoon
Life of this patent
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AssigneeSamsung Electro-Mechanics Co., Ltd.
InventorsChan Wang Park, Joon Ho Yoon
Estimating the term…
Disclosed is a method of manufacturing a semiconductor device package, comprising the steps of forming a patterned photoresist film with windows for exposing a plurality of connection bump areas on a conductive substrate, forming metal plating layers on the connection bumps area using the photoresist film, and forming first gold plating layers on the metal plating layers. The metal plating layers prevent the diffusion of the first gold plating layers into the conductive substrate. The method of manufacturing the semiconductor device package according to the present invention forms high-qualified conductive layers on the connection bumps by a simplified manufacturing process. Further, connection bumps having an upper part in an almost hemispherical shape are formed on the first gold plating layers, thereby improving the reliability of the semiconductor device package.
A method of manufacturing a semiconductor device package with a plurality of connection bumps, said method comprising the steps of:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
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Manufacture or treatment: using temporary auxiliary substrates
Interconnections or connectors in packages: bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
Characterised by their shape or disposition: the semiconductor body being completely enclosed
Connecting or disconnecting: of bond wires
Term end not estimated
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device package, and more particularly to a method of manufacturing a semiconductor device package, in which an electrode surface is formed on a conductive layer of a conductive substrate, thereby miniaturizing the semiconductor device package and simplifying its manufacturing process.
2. Description of the Related Art
The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a cross-sectional view of a conventional semiconductor device package;
FIG. 2 is a cross-sectional view of a semiconductor device package, which is obtained by a manufacturing method in accordance with the present invention; and
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the annexed drawings.
FIG. 2 is a cross-sectional view of a diode package 60, which is obtained by a manufacturing method in accordance with the present invention.
With reference to FIG. 2, the diode package 60 comprises a diode 50. The diode 50 comprises an upper terminal 55 formed on its upper surface and a lower terminal (not shown) formed on its lower surface. Herein, the lower terminal is formed throughout the whole lower surface of the diode 50. Similarly to the conventional semiconductor device package of FIG. 1, the lower terminal of the diode 50 is directly mounted on a connection bump 38b, and the upper terminal 55 of the diode 50 is connected to another connection bump 38a by a wire 47. Herein, gold (Au) plating layers 46a and 46b are formed on each of the connection bumps 38a and 38b, thereby forming a conductive layer of high quality on the connection bumps 38a and 38b.