Mask repattern process
AssigneeMicron Technology, Inc.
InventorWarren M. Farnworth
Life of this patent
Estimating the term…
Abstract
The present invention relates to an improved method for forming a UBM pad and solder bump connection for a flip-chip which eliminates at least two mask steps required in standard UBM pad forming processes when repatterning the bond pad locations.
Claims16
A method of forming portions of circuits connected to bond pads of a semiconductor device, said semiconductor device having circuitry, having at least one surface, and having at least a portion of a circuit on a portion of said at least one surface of said semiconductor device connected to a portion of said circuitry and terminating in said bond pad, said portion of at least one circuit having a portion thereof covered by a first passivation layer while said bond pad remains substantially free of said first passivation layer, said method
- forming a trace of solder wettable material from said bond pad of said circuit to another location on said at least one surface of said semiconductor device, said trace of said solder wettable material contacting a portion of said bond pad and extending over a portion of said at least one first passivation layer, said trace of said solder wettable material having a first surface and a second surface, a portion of said second surface contacting said bond pad;
- forming a second passivation layer over said portion of said at least one surface of said semiconductor device and said trace of said solder wettable material;
- and
- removing a portion of said second passivation layer to form a sloped-wall via through said second passivation layer extending to a portion of said first surface of said trace of solder wettable material at said another location on said at least one surface of said semiconductor device.
A metallization forming method for a semiconductor device, said semiconductor device having circuitry and having at least one surface, said semiconductor device including at least a portion of a solder wettable trace on at least a portion of said at least one surface connected to at least a portion of said circuitry, said semiconductor device having at least one passivation layer over at least a portion of said at least a portion of one solder wettable trace on said at least a portion of said at least one surface, said method comprising:
- removing a portion of said at least one passivation layer for forming a sloped-wall via;
- and
- exposeing portion of said at least one solder wettable trace.
A manufacturing method for a semiconductor device, said semiconductor device having integrated circuitry and a portion of a trace connected to said integrated circuitry, said trace having a bond pad connected thereto, said method comprising:
- forming at least one first passivation layer over a portion of said trace while said bond pad remains substantially free of said at least one passivation layer;
- forming another trace in contact with at least a portion of said bond pad of said at least one portion of said trace, a portion of said another trace extending over a portion of said at least one first passivation layer, said another trace having an upper surface;
- removing a portion of said second passivation layer for forming a portion of a sloped-wall via through said at least one second passivation layer extending to a portion of said upper surface of said another trace;
- and
- forming a solder mass having a portion extending into said sloped-wall via contacting said portion of said upper surface of said another trace.
Dependencies are inferred from the claim text.