Methods for transistor gate formation using gate sidewall implantation
AssigneeTexas Instruments Incorporated
InventorsF. Scott Johnson, Tad Grider, Benjamin P. McKee
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Abstract
Methods are disclosed for semiconductor device fabrication in which MOS transistor gates are to be formed. Polysilicon gate structures and sidewall spacers are formed, with upper portions of the gate sidewalls exposed. Angled implantation processing is employed to impart dopants to the top and exposed sidewall portions of the gate structure to mitigate poly depletion.
Claims23
A method of forming a transistor gate in a semiconductor device, the method comprising:
- forming a polysilicon gate structure over a semiconductor substrate, the polysilicon gate structure comprising a top and a sidewall;
- and
- doping the polysilicon gate structure using an angled implantation process providing dopants to at least an upper portion of the sidewall.
A method of forming a transistor gate in a semiconductor device, the method comprising:
- forming a polysilicon gate structure over a semiconductor substrate, the polysilicon gate structure comprising a top and a sidewall;
- forming a sidewall spacer adjacent a lower portion of the sidewall proximate the substrate leaving an upper portion of the sidewall exposed;
- and
- providing dopants to at least the exposed upper portion of the sidewall.
A method of fabricating transistors in a semiconductor device, the method comprising:
- forming a polysilicon gate structure over a semiconductor substrate, the polysilicon gate structure comprising a top and sidewalls extending from the top toward the semiconductor substrate;
- depositing spacer material over the polysilicon gate structure and the semiconductor substrate;
- selectively removing a portion of the spacer material using a first etch process to form sidewall spacers adjacent the sidewalls, the sidewall spacers covering power portions of the sidewalls and exposing upper portions of the sidewalls, the top of the polysilicon gate structure, and the semiconductor substrate in at least one prospective source/drain region;
- performing a source/drain implantation at an angle to dope the polysilicon gate structure and the exposed semiconductor substrate in the at least one prospective source/drain region;
- removing a remaining portion of the spacer material using a second etch process;
- and
- performing an LDD implantation to further dope the polysilicon gate structure and the exposed semiconductor substrate in the at least one prospective source/drain region.
Dependencies are inferred from the claim text.