Low voltage power MOSFET device and process for its manufacture

#This invention relates to power MOSFET devices and their methods of manufacture, and more specifically relates to such devices with reduced RDSON, reduced gate capacitance and increased gate breakdown voltage.

#In present trench type power MOSFET devices, a vertical gate oxide is formed simultaneously within the vertical walls of the trench and at the trench bottom. In order to provide a low RDSON, the vertical oxide should be relatively thin. However, the gate to drain capacitance is determined by the thickness of the gate oxide at the trench bottom, and the gate breakdown voltage VGSMAX is limited by the curvatures of the oxide at the trench bottom corner. Thus, the desire for a thin vertical gate oxide for low RDSON is contradictory to the need of a thick oxide at the bottom of the trench for improved VGSMAX and a low gate to drain capacitance. It would be desirable to harmonize these trade-offs.

#A further problem exists in present trench type power MOSFETS due to the conventional formation of the channel and source diffusions. Thus, these regions are usually formed by an implant followed by the diffusion. The implants are known to cause surface damage which extends to a particular depth, depending on the process variables. Therefore, the vertical channel, which extends from the point at which the source intersects the trench wall to the bottom of the channel diffusion, will include damaged silicon caused by the earlier implants. This then increases threshold voltage and increases the channel resistance. It would be desirable to avoid the influence of implant damage on the conduction channel of the device.

#FIG. 1A is a cross-section of a trench with a P−−/N−−implant to reduce Miller capacitance.

#FIG. 1B shows an alternative embodiment to the structure of FIG. 1A.

#FIG. 2 is a cross-section of one cell element of a planar geometry chip with the novel P−−/N−−implant.

#Referring first to FIG. 1A, there is shown in cross-section, a very small portion of a trench MOSFET at an early stage of its manufacture. Thus, an N+chip 10 of monocrystalline silicon is first prepared and an N−layer 11 of epitaxially grown silicon is formed thereon. A P−dopant is then implanted and diffused into the top of layer 11 to form P−channel diffusion 12 to a given depth. Thereafter, an N+source impurity is implanted through a suitable mask to form spaced N+source regions such as source region 13 which are also diffused to a given depth. Source region 13 may have any desired topology and can be a stripe or a cell or the like.

#Thereafter, trenches such as trench 20 are etched in the silicon, and a silicon dioxide gate layer 21 having a thickness of about 320 Å is grown along the walls and bottom of the trench 20. A conductive polysilicon gate 22 is formed within trench 20 and the top of the polysilicon 22 is capped with an oxide cap 23.

#A source electrode 24 is then formed over the top surface of the device and in contact with source regions 13 and channel region 12. A drain metal 25 is also applied to the bottom of body 10.