Polycrystalline silicon thin film transistor and method for fabricating the same

A method for fabricating a thin film transistor device, comprising the steps of:

• forming a buffer layer on a substrate;
• forming an island-shaped polycrystalline silicon active layer on the buffer layer to include first, second, and third areas;
• forming a gate insulation layer on the buffer layer to cover the island-shaped polycrystalline silicon active layer;
• forming a dual-gate electrode on the gate insulation layer to correspond to the first areas of the island-shaped polycrystalline silicon active layer, the dual-gate electrode includes a first gate electrode and a second gate electrode;
• forming a photo resist pattern completely covering a portion of the gate insulation layer between the first and second gate electrodes;
• removing the photo resist pattern from the gate insulation layer and the first and second gate electrodes;
• forming an interlayer insulator on the gate insulation layer to cover the first and second gate electrodes;
• forming a gate contact hole to expose a portion of the dual-gate electrode by partially etching the interlayer insulator;
• forming source and drain contact holes to penetrate both the interlayer insulator and the gate insulation layer to expose the third areas of the island-shaped polycrystalline silicon active layer;
• and
• forming source and drain electrodes and a third gate electrode on the interlayer insulator,
• wherein the source and drain electrodes contact the third areas of the polycrystalline silicon active layer through the source and drain contact holes, and the third gate electrode contacts the exposed portion of the dual-gate electrode through the gate contact hole.

A method for fabricating a thin film transistor device, comprising the steps of:

• forming a buffer layer on a substrate;
• forming an island-shaped polycrystalline silicon active layer on the buffer layer to include first, second, and third areas;
• forming a gate insulation layer on the buffer layer to cover the island-shaped polycrystalline silicon active layer;
• forming a dual-gate electrode on the gate insulation layer to correspond with the first areas, the dual-gate electrode includes a first gate electrode and a second gate electrode;
• forming a photo resist pattern on a portion of the gate insulation layer between the first and second gate electrodes to fully cover the first and second gate electrodes, fill a space between the first and second gate electrodes, and partially overlap the third areas;
• removing the photo resist pattern from the gate insulation layer and the first and second gate electrodes;
• forming an interlayer insulator on the gate insulation layer to cover the first and second gate electrodes;
• forming gate contact holes to expose a portion of the dual-gate electrode by partially etching the interlayer insulator;
• forming source and drain contact holes to penetrate both the interlayer insulator and the gate insulation layer to expose the third areas;
• and
• forming source and drain electrodes and a third gate electrode on the interlayer insulator,
• wherein the source and drain electrodes contact the third areas of the polycrystalline silicon active layer through the source and drain contact holes, and the third gate electrode contacts the exposed portion of the dual-gate electrode through the gate contact hole.

A thin film transistor device, comprising:

• a semiconductor layer including first and second highly doped areas, third lightly doped area, and fourth and fifth undoped intrinsic areas;
• a gate insulation layer covering the semiconductor layer;
• first and second gate electrodes on the gate insulation layer and over the semiconductor layer;
• an interlayer insulator formed on the gate insulation layer and covering the first and second gate electrodes, wherein the interlayer insulator and the gate insulation layer have contact holes penetrating therethrough to expose the first and second highly doped areas;
• and
• source and drain electrodes on the interlayer insulator and contacting the first and second highly doped areas through the contact holes, respectively.

A thin film transistor device, comprising:

• a semiconductor layer including first and second highly doped areas, third, fourth and fifth lightly doped areas, and sixth and seventh undoped intrinsic areas;
• a gate insulation layer covering the semiconductor layer;
• first and second gate electrodes on the gate insulation layer and over the semiconductor layer;
• an interlayer insulator formed on the gate insulation layer and covering the first and second gate electrodes, wherein the interlayer insulator and the gate insulation layer have contact holes penetrating therethrough to expose the first and second highly doped areas;
• and
• source and drain electrodes on the interlayer insulator and contacting the first and second highly doped areas through the contact holes, respectively.