Transistor and associated driving device
AssigneeHannstar Display Corp.
InventorPo-Sheng Shih
Life of this patent
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AssigneeHannstar Display Corp.
InventorPo-Sheng Shih
Estimating the term…
A method of forming a thin film transistor and its associated driver. A polysilicon layer, a gate oxide layer and a gate layer are formed on a substrate. A photoresist layer comprising of a top section and a base section is formed over the gate layer. The top section of the photoresist layer patterns out a thin film transistor gate while the base section outside the top section patterns out a lightly doped region or undoped region on each side of the gate. Complementary metal-oxide-semiconductor drivers are formed on each side of the thin film transistor.
A method of forming a thin film transistor, comprising:
A method of forming a thin film transistor and its associated driver, comprising:
A method of forming a thin film transistor and its associated driver, comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
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Of multiple TFTs: using masks, e.g. half-tone masks
Characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes: characterised by the doping profiles, e.g.…
Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless…
Characterised by multiple TFTs: wherein the TFTs are in active matrices
Term end not estimated
This application claims the priority benefit of Taiwan application serial no. 90110253, filed on Apr. 30, 2001.
1. Field of Invention
The present invention relates to a method of manufacturing a thin film transistor and associated driving device. More particularly, the present invention relates to a method of manufacturing a thin film transistor and associated driving device by forming a photoresist layer having a base section and a top section. The top section patterns out thin film transistor's gate while the base section patterns out a lightly doped drain (LDD) or undoped region so that one less masking step is required.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,
FIGS. 1A through 1C are schematic cross-sectional views showing the steps for producing a conventional thin film transistor with lightly doped drain regions;
FIGS. 2A through 2C are schematic cross-sectional views showing the steps for fabricating a conventional thin film transistor with lightly doped structures and its associated driver,
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
FIGS. 3A through 3C are schematic cross-sectional views showing the steps for producing a thin film transistor with lightly doped drain regions according to one preferred embodiment of this invention. As shown in FIG. 3A, an insulating substrate 300 is provided. A polysilicon layer 302, a gate oxide layer 304 and a gate layer 306a are sequentially formed over the insulating substrate 300. A patterned photoresist layer 308 having a top section 308a and a base section 308b is formed over the gate layer 306a. The patterned photoresist layer 308 later serves as a mask for forming a gate electrode 306b (shown in FIG. 3B) and a lightly doped drain region 312 (shown in FIG. 3C). The base section 308b of the photoresist layer 308 has a width greater than the top section 308a of the photoresist layer 308. The top section 308a of the photoresist layer 308 patterns out the gate electrode 306b (shown in FIG. 3B). The base section 308b outside the top section 308a patterns out the lightly doped drain regions 312 (shown in FIG. 3C).
A portion of the gate layer 306a is removed using the patterned photoresist layer 308 as a mask. A heavy implantation 314 is next carried out to form heavily doped regions 310 in the polysilicon layer 302. The heavily doped regions 310 can be heavily doped n-type regions, for example.