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US 2003/0194830 A1Published application
Semiconductor chip package and manufacturing method thereof
AssigneeAdvanced Semiconductor Engineering, Inc.
InventorChih Ming Chung
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AssigneeAdvanced Semiconductor Engineering, Inc.
InventorChih Ming Chung
Estimating the term…
This invention provides a method for manufacturing a semiconductor chip package which mainly utilizes a substrate having a organic surface protection thereon to package a central-pad chip. In the encapsulating process, since the molding flash is completely formed on the surface of the organic surface protection, the molding flash can be easily removed together with the organic surface protection without damaging the substrate surface. This invention further provides a method for manufacturing the substrate.
A method for manufacturing a semiconductor chip package, the method comprising:
A method for manufacturing a substrate comprising:
A substrate having an upper surface adapted for receiving a semiconductor chip and a lower surface opposing to the upper surface, the substrate comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Backward citations are indexed for grants only.
Package configurations: characterised by the relative positions of pads or connectors relative to package parts
The semiconductor body being completely enclosed: forming a chip-scale package [CSP]
Comprising metals or metalloids, e.g. silver: comprising gold [Au]
On the same surface: die-attach connectors and bond wires
Term end not estimated
1. Field of the Invention
This invention relates to a package for a central-pad chip and a manufacturing method thereof, and more particularly, to an improved substrate and a method for dealing with molding flash.
2. Description of the Related Art
Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.
FIG. 1 is a cross-sectional view of a conventional package for use in packaging a central-pad chip;
FIG. 2 is a cross-sectional view of a substrate according to a first embodiment of the present invention;
FIG. 2 shows a substrate 200 according to one embodiment of the present invention.
The substrate 200 is characterized by having an organic surface protection 230 formed on the solder mask 222 of a printed circuit board 220 and around a slot 224 defined in the substrate. Preferably, the organic surface protection is made of an organic solderability preservative (OSP). The lower surface of the printed circuit board 220 is provided with a plurality of solder pads 226 and chip connection pads 228 electrically connected to the solder pads 226 respectively. The lower surface of the printed circuit board is covered by the solder mask 222 in a manner that the solder pads 226 and the chip connection pads 228 are exposed through the solder mask. The printed circuit board 220 is provided with conductive traces which constitute a network of connection for electrical ground, power and signal lines. Though only one layer of conductor circuits of the printed circuit board 220 is shown in this embodiment, a printed circuit board for use with this invention can include more than two layers of conductor circuits if desired. It should be understood that the printed circuit board 220 may be formed from a core layer made of fiberglass reinforced BT (bismaleimide-triazine) resin, or FR-4 fiberglass reinforced epoxy resin thereby increasing the mechanical strength of the substrate. Alternatively, a polyimide-based substrate may be used.
Preferably, the solder pads 226 and the chip connection pads 228 have a layer of nickel formed on the surface thereof (not shown) and a layer of gold or palladium formed on the nickel layer (not shown). The nickel/gold (or palladium) layer can protect the surfaces of the solder pads 226 and chip connection pads 228 from corrosion or contamination thereby assuring the solder-joint reliability.