Balancing planarization of layers and the effect of underlying structure on the metrology signal
AssigneeTimbre Technologies, Inc.
InventorsNickhil Jakatdar, Xinhui Niu
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AssigneeTimbre Technologies, Inc.
InventorsNickhil Jakatdar, Xinhui Niu
Estimating the term…
The present invention includes a method and system for identifying an underlying structure that achieves improved planarization characteristics of layers while minimizing introduction of random and/or systematic noise to the reflected metrology signal. One embodiment of the present invention is a method of designing underlying structures in a wafer with pads of varying sizes and varying loading factors, and selecting the design of pads that yield a reflected metrology signal closest to the calibration metrology signal and that meet preset standard planarization characteristics. Another embodiment is a method of designing underlying structures with random shapes of varying sizes and varying loading factors. Still another embodiment is the use of periodic structures of varying line-to-space ratios in one or more underlying layers of a wafer, the periodicity of the underlying periodic structure being positioned at an angle relative to the direction of periodicity of the target periodic structure of the wafer. The present invention also includes a system for selecting an underlying structure design that balances planarization and optical metrology objectives for a target structure comprising a wafer fabricator, a planarizer, a layer profiler, an optical metrology device, and a selector for the selecting the design of underlying structure that yields a reflected metrology signal closest to the calibration metrology signal and where the planarized surfaces meet preset standard planarization characteristics.
A method of designing underlying structures in a wafer that balances planarization and optical metrology characteristics, the method comprising:
A method of fabricating underlying structures in a wafer that balances planarization and optical metrology characteristics, the method comprising:
A method of fabricating underlying structures in a wafer that balances planarization and optical metrology characteristics, the method comprising:
A method of fabricating underlying structures in a wafer that balances planarization and optical metrology characteristics, the method comprising:
A method of designing underlying structures in a wafer that balances planarization and optical metrology characteristics, the method comprising:
A method of designing underlying structures in a wafer that balances planarization and optical metrology characteristics, the method comprising:
A method of selecting an underlying structure design that balances planarization and optical metrology objectives for a target structure, the method comprising:
A system for selecting an underlying structure design that balances planarization and optical metrology objectives for a target structure, the system comprising:
A computer-readable storage medium containing computer executable code to select an underlying structure design that balances planarization and optical metrology objectives for a target structure by instructing a computer to operate as follows:
A method of providing a service for selecting the selecting an underlying structure design that balances planarization and optical metrology objectives for a target structure, the method comprising:
Dependencies are inferred from the claim text.
From the US filing history. Foreign family members aren’t listed.
Backward citations are indexed for grants only.
Structural arrangements therefor: interconnections for measuring or testing, e.g. probe pads
Scattering, i.e. diffuse reflection: diffraction
Characterised by the material or shape of the object to be examined: semiconductor wafers
Characterised by the material or shape of the object to be examined: inspecting patterns on the surface of objects
Term end not estimated
1. Field of Invention
This invention is in the field of manufacture of semiconductor devices. More particularly, this invention relates to a method and system of fabricating underlying structures to improve planarization characteristics of layers while minimizing introduction of random and/or systematic noise by the underlying structures to the metrology signal.
2. Related Art
FIG. 1A is an architectural diagram illustrating the “dishing” effects of the CMP process on a layer of a wafer.
FIG. 1B is an architectural diagram illustrating the “erosion” effects of the CMP process on a layer of a wafer.
FIG. 2 is an architectural diagram illustrating the use of an optical metrology system to acquire critical dimension (CD) data off target periodic structures.
The present invention includes a method for identifying, for a given target structure, the design, distribution, and density of fill shapes of the underlying structures and/or the arrangement of the patterned underlying structures that will minimize the introduction of random or systematic noise to the reflected metrology signal off the target structure.
A summary of the process for the present invention, described in detail in FIG. 8, is provided here to facilitate the descriptions of figures that follow. Initially, the CMP and optical metrology signal design criteria for the target structure are set. A target structure is the patterned structure of a layer of a wafer that is measured using optical metrology. A predetermined set of underlying structures, including a calibration underlying structure, is designed. Based on the CMP design criteria, a set of pads and/or random shapes of varying size, geometry, and loading factors may be designed in a mask for the underlying structures. Alternatively, a set of periodic underlying structures with varying line-to-space ratios may be designed. The predetermined set of underlying structures and subsequent layers of the wafer are fabricated. A CMP process may be required for one or more of the subsequent layers of the wafer. Whenever a CMP process is involved, the CMP process characteristics of the planarized layer are measured. The target structures in the target layer of the wafer are fabricated. The reflected optical metrology signal from a calibration test area in the target layer of the wafer is measured. Once the calibration reflected optical metrology signal is obtained, reflected optical metrology signals from the other target structures with underlying structures varying in either loading factors or line-to-space ratios are measured.
In an alternative embodiment for periodic underlying structures, the reflected optical metrology signals from the target structures in the target layer may be calculated for both the calibration test area and the other test structures with underlying structures varying in either loading factors or line-to-space ratios. The measured or the calculated reflected optical metrology signals are compared to the calibration reflected optical metrology signal and the best-fitting measured or calculated reflected optical metrology signal is identified. If both of the CMP and optical metrology signal design criteria are met, the underlying structure associated with the target structure identified as having best-fitting signal is selected as the underlying structure for the fabrication run. Otherwise, the process is iterated starting with designing a new set of underlying structures.