Image processing architecture
AssigneeIntel Corporation
InventorsWERNER METZ, TINKU ACHARYA
Life of this patent
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Abstract
A system includes a central processing unit, a bus and circuit. The central processing unit is coupled to the bus and segments an image into at least one text region and at least one graphics region. At least one of the circuit modules is associated with the processing of the text region(s), and at least one of the circuit modules is associated with the processing of the graphics region(s).
Claims21
A computer system comprising:
- a central processing unit to segment an image into at least one text region and at least one graphics region;
- a bus coupled to the central processing unit;
- circuit modules, at least one of the circuit modules being associated with the processing of said at least one text region and at least one of the circuit modules being associated with the processing of said at least one graphics region.
A bridge comprising:
- an interface to receive indications of the boundaries of text regions and graphics regions of an image from a central processing unit;
- a central processing unit to segment an image into at least one text region and at least one graphics region;
- a bus;
- and
- circuit modules coupled to the bus, some of the circuits being associated with the processing of said at least one text region and some of the circuit modules being associated with the processing of said at least one graphics region.
A method comprising:
- segmenting an image into at least one text region and at least one graphics region;
- using a first group of hardware modules to process said at least one text region of the image;
- programming the hardware modules of the first group with a first processing order among the hardware modules of the first group to define a text processing chain;
- using at second group of hardware modules to process said at least one graphics region of the image;
- and
- programming the hardware modules of the second group with a second processing order among the hardware modules of the second group to define a graphics processing chain.
The method of claim 21, wherein programming the hardware modules of the first group to define an arbitration hierarchy on the bus among the hardware modules of the first group.
The method of claim 21, wherein at least one of the modules is part of both the first and second groups.
Dependencies are inferred from the claim text.