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AssigneeAdvantest Corporation
InventorsToshiyuki Okayasu, Shinya Sato
Estimating the term…
A standard clock 34 is input to a phase comparator 52 and a phase controller 56. The ring oscillator 50 oscillates a shift clock 70 having a same cycle as the standard clock 34. The phase comparator 52 matches the downward shift of the shift clock 70 with the downward shift of the standard clock 34 to output a shift clock 72. The shift clock 72 is supplied to the pulse inserter 54. The phase controller 56 receives the standard clock 34 and generates a phase control signal 74 indicating cycles of the shift clock 72 to which the insert-pulses are inserted among a plurality of cycles of the shift clock 72. The pulse inserter 54 inserts the insert-pulses to the cycles of the shift clock indicated by the phase control signal 74. The phase-lock unit 58 generates a delay clock 82 by delaying the phase of the shift clock 70 oscillated by the ring oscillator 50 with respect to the phase of the standard clock, based on the standard clock and the shift clock 76 including the insert-pulses.
A delay clock generating apparatus generating a delay clock which is delayed by a predetermined time with respect to a standard clock, comprising:
A method of measuring a delay time of a delay line, said delay line comprising an input terminal and an output-terminal for a standard clock, said output terminal being connected to a data input of a flip-flop circuit operated by a delay clock having a predetermined delay time with respect to said standard clock, comprising:
A delay time measuring apparatus measuring a delay time of a delay line, comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
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Concerning mainly the controlled oscillator of the loop: the oscillator comprising a ring oscillator
Stimuli generation or application of test patterns to the device under test [DUT]: timing generation or clock distribution
Automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or
Measuring electric variables
Term end not estimated
This patent application claims priority based on a Japanese patent application, H11-95941 filed on Apr. 2, 1999, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a delay clock generating apparatus which generates a delay clock, and more particularly to a delay clock generating apparatus which is incorporated in a delay signal generator of a semiconductor testing device, which tests a semiconductor device.
FIG. 1 is a block diagram of an example of the delay line 176 in the semiconductor testing device, that delays a test pattern by a predetermined delay time;
FIG. 2 is a block diagram of a conventional structure of the semiconductor testing device in which an output signal output from the waveform formatter 12 which is delayed with respect to a signal generated by the pattern generator 10 is measured;
FIG. 3 is a block diagram of the semiconductor testing device for testing the DUT 22;
The invention will now be described based on the preferred embodiments, which do not intend to limit the scope of the present invention, but exemplify the invention. All of the features and the combinations thereof described in the embodiment are not necessarily essential to the invention.
FIG. 3 is a block diagram of a semiconductor testing device, for testing a device under test (DUT) 22. The semiconductor testing device includes a pattern generator 10, a delay signal generator 24, a signal input/output unit 18 and a comparator 20. The delay signal generator 24 has a waveform formatter 12 and a timing generator 14. The DUT 22 is connected to the signal input/output unit 18 while being tested.
The pattern generator 10 generates an input pattern 33 and a standard clock 34 which are to be input to the DUT 22, and supplies them to the delay signal generator 24. The input pattern 33 is input to the waveform formatter 12 and the standard clock 34 is input to the timing generator 14. Inside the timing generator is a delay clock generator, not shown in the drawings, and a delay line, shown in FIG. 1 as 176. Data of combinations of delay elements for generating a predetermined delay time are previously stored in a memory 196 of the delay line 176. The data in this embodiment are obtained based on a delay clock having a predetermined delay time, generated by the delay clock generator.