Distributed link module architecture

#The present invention generally relates to multi-core central processing units and particularly relates to the link layout architecture for a central processing unit.

#New computer architectures, especially those utilizing multiprocessor technologies, use high-speed serial point-to-point link interconnect strategies. These links typically have high frequency (2 GHz plus) signaling that, due to losses in the transmission media (printed circuit board and connectors), results in small signals being received at the input of the destination chip. These small amplitude signals are normally sent differentially to increase the link reliability and reduce the link's sensitivity to common-mode noise. A link module typically consists of one to twenty bits of data operating in bidirectional mode. A link module also typically includes timing recovery circuitry (multi-phase lock loop) and voltage restore circuitry (integrating receivers). This architecture has many advantages.

#Among these advantages, the architecture provides a simpler chip floor plan for large, multi-core, multi-link central processing units. These advantages further include centralized link timing recovery and simplified link to cross bar synchronization. Still further advantages of this architecture include fewer phase lock loops required for clock generation, and a shared cross bar switch, link, and core clock generation. The particulars of this architecture, however, are dictated at least in part by the high-speed link requirements.

#The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein:

#FIG. 1 is a block diagram of existing link layout architecture according to previous technology;

#FIG. 2 is a block diagram of existing electrical architecture for a link module according to previous technology;

#The following description of the preferred embodiment(s) is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses.

#Referring to FIG. 3, a link layout architecture 48 according to the present invention is shown. In this scheme, only the bit receivers and bit output drivers 50 (with their pre-emphasis circuitry) are placed at a distance from the cross bar switch 52. The remaining link module circuitry for all the links is placed near to the cross bar switch 52. The remote link circuitry is much smaller than the existing methodology, which allows this circuitry to be more easily integrated into the sea of cache random access memory 54. As shown in FIG. 3, the bit receivers and bit output drivers 50 are grouped into 4 regions. There could, however, be more regions since there are no major constraints as to where these remote analog regions could be placed other than the C4 and package constraints. Therefore, these remote analog regions, being smaller and less constrained, can be optimized in placement for the C4 bumps and package.

#A feature of this architecture 48 is that the remote communication between the cross bar/link logic in the center of the die and the remote analog circuitry is digital asynchronous. The remote digital asynchronous signals can be routed and buffered across the die without timing or skew penalty.