Diversity receiver with joint baud clock recovery

In a diversity receiver having first and second channels, said first channel having a first tuner and said second channel having a second tuner, a method comprising:

• providing a first local oscillator having an output terminal;
• coupling said output terminal of said first local oscillator to said first tuner;
• and
• coupling said output terminal of said first local oscillator to said second tuner.

In a diversity receiver having first and second channels with respective first and second tuners, each of said first and second tuners having a respective tuner output terminal, said first tuner further having a first AGC control input terminal, and said second tuner further having a second AGC control input terminal, a joint AGC method comprising:

• sensing a first signal level at the output terminal of said first tuner to provide a first sensed signal level;
• sensing a second signal level at the output terminal of said second tuner to provide a second sensed signal level;
• generating a first AGC control signal responsive to said first sensed signal level and said second sensed signal level;
• and
• coupling said first AGC control signal to said first AGC control input terminal of said first tuner.

In a diversity receiver with first and second channels having respective first and second digital signals therein, each of said first and second digital signals having respective first and second baud clock timing, said first baud clock timing defining the timing for sampling said first digital signal to recover a data symbol in said first channel, said second baud clock timing defining the timing for sampling said second digital signal to recover a data symbol in said second channel, said first and second baud clock timing having a common baud clock frequency, an apparatus for recovering said first and second baud timing comprising:

• a joint processing circuit responsive to said first and second digital signals;
• a first baud clock recovery circuit responsive to said joint processing circuit and said second digital signal for recovering said first baud clock timing in said first channel;
• a second baud clock recovery circuit responsive to said joint processing circuit and to said first digital signal for recovering said second baud clock timing in said second channel,
• whereby said first baud clock recovery circuit is responsive to said second baud clock recovery circuit to recover said first baud clock timing.

In a diversity receiver with first and second channels having respective first and second digital signals therein, each of said first and second digital signals having respective first and second baud clock timing, said first baud clock timing defining the timing for sampling said first digital signal to recover a data symbol in said first channel, said second baud clock timing defining the timing for sampling said second digital signal to recover a data symbol in said second channel, said first and second baud clock having a common baud clock frequency, said first and second channels including respective first and second variable delay elements for introducing respective first and second delays into said first and second digital signals therein, a skew corrector apparatus for recovering said first and second baud timing, said skew corrector apparatus comprising:

• a correlator for computing a first correlation value between said first digital signal and said second digital signal;
• means for shifting said first digital signal in said first variable delay memory by a whole multiple of the clock period of said common baud clock frequency to form a first delayed first digital signal;
• means for using said correlator to compute a second correlation value between said first delayed first digital signal and said second digital signal;
• and
• means for setting a value of delay for said first variable delay to correspond to the greater of said first and second correlation values.

In a diversity receiver with first and second channels having respective first and second digital signals therein, each of said first and second digital signals having respective first and second baud clock timing, said first baud clock timing defining the timing for sampling said first digital signal to recover a data symbol in said first channel, said second baud clock timing defining the timing for sampling said second digital signal to recover a data symbol in said second channel, said first and second baud clock having a common baud clock frequency, said first and second channels including respective first and second variable delay elements for introducing respective first and second delays into said first and second digital signals therein, a method for correcting for whole baud skew in said first and second baud timing, said method comprising:

• computing a first correlation value between said first digital signal and said second digital signal;
• shifting said first digital signal in said first variable delay memory by a whole multiple of the clock period of said common baud clock frequency to form a first delayed first digital signal;
• computing a second correlation value between said first delayed first digital signal and said second digital signal;
• and
• selecting a value of said first variable delay corresponding to the greater of said first and second correlation values.

In a diversity receiver with first and second channels having respective first and second digital signals therein, each of said first and second digital signals having respective first and second baud clock timing, said first baud clock timing defining the timing for sampling said first digital signal to recover a data symbol in said first channel, said second baud clock timing defining the timing for sampling said second digital signal to recover a data symbol in said second channel, said first and second baud clock timing having a common baud clock frequency, said first and second channels including respective first and second variable delay elements for introducing respective first and second delays into said first and second digital signals therein, an apparatus comprising:

• a joint processing circuit responsive to said first and second digital signals;
• a first baud clock recovery circuit responsive to said joint processing circuit and said second digital signal for recovering said first baud clock timing in said first channel;
• a second baud clock recovery circuit responsive to said joint processing circuit and to said first digital signal for recovering said second baud clock timing in said second channel, and
• a skew corrector apparatus responsive to said first and second recovered baud clock timing from said first and second baud clock recovery circuits, said skew corrector apparatus comprising:
• a correlator for computing a first correlation value between said first digital signal and said second digital signal;
• means for shifting said first digital signal in said first variable delay memory by a whole multiple of the clock period of said common baud clock frequency to form a first delayed first digital signal;
• means for using said correlator to compute a second correlation value between said first delayed first digital signal and said second digital signal;
• and
• means for setting a value of delay for said first variable delay to correspond to the greater of said first and second correlation values.

In a diversity receiver with first and second channels having respective first and second digital signals therein, each of said first and second digital signals having respective first and second baud clock timing, said first baud clock timing defining the timing for sampling said first digital signal to recover a data symbol in said first channel, said second baud clock timing defining the timing for sampling said second digital signal to recover a data symbol in said second channel, said first and second baud clock having a common baud clock frequency, said first and second channels including respective first and second variable delay elements for introducing respective first and second delays into said first and second digital signals therein, a method for recovering said first and second baud timing, said method comprising:

• recovering said first baud clock timing in said first channel responsive to said first and second digital signals;
• recovering said second baud clock timing in said second channel responsive to said first and second digital signals;
• computing a first correlation value between said first digital signal and said second digital signal;
• shifting said first digital signal in said first variable delay memory by a whole multiple of the clock period of said common baud clock frequency to form a first delayed first digital signal;
• computing a second correlation value between said first delayed first digital signal and said second digital signal;
• and
• selecting a value of said first variable delay corresponding to the greater of said first and second correlation values.

In a diversity receiver with first and second channels having respective first and second digital signals therein, said first and second channels of said diversity receiver further including respective first and second phase locked loops, said first phase locked loop including a first controlled oscillator, and a first phase detector responsive to said first digital signal for providing a first phase error signal, said second phase locked loop including a second controlled oscillator, and a second phase detector responsive to said second digital signal for providing a second phase error signal, a joint loop filter for cross coupling said first and second phase locked loops, said joint loop filter comprising:

• an adder having respective first and second input terminals, and an output terminal;
• said first phase error signal being coupled to said first input terminal of said adder;
• said second phase error signal being coupled to said second input terminal of said adder;
• and
• said output terminal of said adder being coupled to said first and second controlled oscillators.

In a diversity receiver with first and second channels having respective first and second digital signals thereinsaid first and second channels of said diversity receiver further including respective first and second phase locked loops, said first phase locked loop including a first controlled oscillator, and a first phase detector responsive to said first digital signal for providing a first phase error signal, said second phase locked loop including a second controlled oscillator, and a second phase detector responsive to said second digital signal for providing a second phase error signal, a joint loop filter for cross coupling said first and second phase locked loops, said joint loop filter comprising:

• first, second and third adders having respective first and second input terminals, and a respective output terminal;
• said first phase error signal being coupled to said first input terminal of said first adder and to said first input of said second adder;
• said second phase error signal being coupled to said second input terminal of said first adder and to said first input terminal of said third adder;
• said output terminal of said first adder being coupled to the second input terminal of said second adder and to the second terminal of said third adder;
• said output terminal of said second adder being coupled to said first controlled oscillator;
• and
• said output terminal of said third adder being coupled to said second controlled oscillator.

In a diversity receiver with first and second channels having respective first and second digital signals thereinsaid first and second channels of said diversity receiver further including respective first and second phase locked loops, said first phase locked loop including a first controlled oscillator and a first phase detector responsive to said first digital signal for providing a first phase error signal, said second phase locked loop including a second controlled oscillator and a second phase detector responsive to said second digital signal for providing a second phase error signal, a joint loop filter method for cross coupling said first and second phase locked loops, said joint loop filter method comprising:

• adding said first and second phase error signals to provide a joint phase error signal;
• combining said joint phase error signal with said first phase error signal to provide a first joint loop filter output;
• combining said joint phase error signal with said second phase error signal to provide a second joint loop filter output;
• coupling said first loop filter output to said first controlled oscillator;
• and
• coupling said second loop filter output to said second controlled oscillator.

In a diversity receiver with first and second channels having respective first and second digital signals therein, a joint equalization filter comprising:

• a first equalization filter coupled to said first channel of said diversity receiver, said first equalization filter having a first plurality of coefficients corresponding to a first plurality of taps;
• a second equalization filter;
• coupled to said second channel of said diversity receiver said second equalization filter having a second plurality of coefficients corresponding to a second plurality of taps;
• and
• a dynamic tap allocation circuit responsive to said first and second digital signals for setting at least a portion of said first plurality of coefficients to zero and for setting at least a portion of said second plurality of coefficients to zero.

In a diversity receiver with first and second channels having respective first and second digital signals therein, a method of joint equalization, said method comprising:

• providing a first equalization filter coupled to said first channel of said diversity receiver, said first equalization filter having a first plurality of coefficients corresponding to a first plurality of taps;
• providing a second equalization filter;
• coupled to said second channel of said diversity receiver said second equalization filter having a second plurality of coefficients corresponding to a second plurality of taps;
• and
• allocating filter taps between said first and second channels responsive to said first and second digital signals by setting at least a portion of said first plurality of coefficients to zero and at least a portion of said second plurality of coefficients to zero.

In a diversity receiver with first and second channels having respective first and second digital signals therein, a joint equalization filter comprising:

• a multiplexor having first and second input terminals and an output terminal, said first input terminal being coupled to said first channel and said second input terminal being coupled to said second channel, said multiplexor adapted for alternatively selecting said first and second channels so as to interleave one digital sample of said first digital signal with one digital sample of said second digital signal;
• an equalizer filter coupled to said output terminal of said multiplexor, said equalization filter having a first plurality of coefficients corresponding to a first plurality of taps;
• and
• a tap allocation circuit for setting at least a portion of said first plurality of coefficients to zero.

In a diversity receiver with first and second channels having respective first and second digital signals therein, a method of joint equalization, said method comprising:

• multiplexing one digital sample of said first digital signal with one digital sample of said second digital signal to provide an interleaved digital signal;
• providing an equalizer filter coupled to said interleaved digital signal, said equalization filter having a first plurality of coefficients corresponding to a first plurality of taps;
• and
• allocating filter taps between said first and second channels responsive to said first and second digital signals by setting at least a portion of said first plurality of coefficients to zero.