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AssigneeKoninklijke Philips Electronics N.V.
InventorWillem M.J. Coene
Estimating the term…
A partial response maximum likelihood (PRML) bit detection apparatus is disclosed for deriving a bit sequence from an input information signal. The apparatus comprises input means for receiving the input information signal, sampling means for sampling the input information signal at sampling instants so as to obtain samples of the input information signal at said sampling instants, conversion means for converting an array of said samples into an array of bits of a first or a second binary value, detection means for repeatedly detecting a state for subsequent sequences of n subsequent bits of said array of bits, said subsequent sequences being obtained by shifting a time window of n subsequent bits each time over one bit in time, means for establishing the best path through the states, and deriving means for deriving a sequence of bits in accordance with the best path through said states. In accordance with the invention, n is larger than 3, and sequences of n subsequent bits having n−1 directly successive bits of the same binary value are allocated to the same state. In a specific embodiment is n an odd number larger than 4. Now, sequences of n subsequent bits having n−2 directly successive bits of the same binary value as the central n−2 bits in such n-bit sequence, are allocated to the same state. This results in an a PRML detection apparatus with reduced complexity.
A partial response maximum likelihood (PRML) bit detection apparatus for deriving a bit sequence from an input information signal, comprising
A partial response maximum likelihood (PRML) bit detection apparatus for deriving a bit sequence from an input information signal, comprising
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Digital recording or reproducing: improvement or modification of read or write signals
Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes: using the Viterbi algorithm or Viterbi processors
Using the Viterbi algorithm or Viterbi processors: implementing add, compare, select [ACS] operations
Joint error correction and other techniques: error control coding in combination with equalisation
Term end not estimated
The invention relates to a partial response maximum likelihood (PRML) bit detection apparatus for deriving a bit sequence from an input information signal, comprises
input means (1) for receiving the input information signal,
sampling means for sampling, at a predetermined sampling frequency, the input information signal at sampling instants ti so as to obtain sample values of the input information signal at said sampling instants ti, said sampling frequency having a relationship with a bit frequency,
A PRML bit detection apparatus with reduced complexity will be described. Partial-Response Maximum-Likelihood (PRML) detection is a candidate to replace the standard technique of Threshold Detection (TD) as used in CD and DVD-like systems. For the new DVR (digital video recorder) system, which is an optical recording/reproduction system, where a d=1 channel code is used, a 3-taps PRML detector has been proposed. Investigations have shown that an increase in the number of taps yields a markedly improved performance in terms of the bit-error-rate (BER). However, this implies also an increase in complexity of the Viterbi-trellis, which is linearly dependent on the number of states in the finite-state-machine (FSM) that is used for a n+1-taps PRML. The number of states Ns amounts to 2 times Nd=1(n) with Nd=1(n) the Fibonacci numbers, i.e. the number of sequences of length n for a d=1 constraint.
The number Ns of states and the number NB of the branches connecting the states in the trellis diagram are shown in Table 1 for some choices of the number of taps. The main drawback of using a 5-taps PRML is its largely increased complexity (+167%) compared to a 3-taps PRML. 1 TABLE 1 Number of states (Ns) and number of branches (NB) of the Finite-State-Machine (FSM) as a function of the number of taps of the PRML detector (for a d = 1 channel code). number of taps Ns NB 3 6 10 5-r.c. 10 16 5 16 26
The finite state diagrams for the 3-taps and 5-taps PRML are shown in FIGS. 1 and 2, respectively. FIG. 3 compares the performance in terms of bit-error-rate (BER) for a d=1 experiment for phase-change recording. The gain between 3-taps and 5-taps is due to differentiation for the short runlengths, i.e. I2 and I3. In the case of the 3-taps PRML, the first bits (or the last bits) of an I2 and an I3 are related to the same state; this implies that the same reference amplitude level is used upon computing the likelihood. In the case of the 5-taps PRML, the runs I2 and I3 follow separate paths through the finite state diagram so that the difference in amplitude level can be accounted for. For the 5-taps PRML, additional states are present in the finite state diagram which are related to the longer runs from I4 on; the 5-taps states (−1)(1)4 and (1)4(−1) on the positive bit-side (+1), and the states (1)4(1) and (1)(−1)4 on the negative bit-side (−1) are visited for the runs I4 and larger, the states (1)5 and (−1)5 are visited for the runs I5 and larger. For the 3-taps PRML, all the runs longer than I3 pass through the states (1)3 or (−1)3.