Data slicer

#The present invention relates to a data slicer for digitalizing a received signal such as a radio signal.

#Japanese Laid-Open Patent Application Tokukaisho 63-90221/1988 (published on Apr. 21, 1988) discloses a digitalization circuit using image sensor output, which includes output means for outputting intermittent image signals from an image sensor for scanning data of the document surface, first digitalizing means for digitalizing image signals outputted from the output means based on the integral value of the image signals, second digitalizing means for digitalizing the image signals outputted from the output means based on a single threshold voltage, and output difference detecting means for detecting the difference between two image signals adjacent to each other of the image signals outputted from the output means, wherein when the output difference detected by the detection means exceeds a predetermined value, a digitalization signal of the first digitalizing means is selected; and when the output difference is at or less than the predetermined value, a digitalization signal of the second digitalizing means is selected.

#An object of the present invention is to provide a data slicer capable of accurately carrying out digitalization of a signal, which is demodulated after being received.

#FIG. 1 is a drawing showing an example of packet data.

#FIG. 2 is a block diagram showing an arrangement example of a data slicer.

#FIG. 3 is a drawing showing an example of switching operation of a data slicer.

#Firstly, FIG. 18 shows a block diagram showing an example of receiving a radio signal of a modulation mode such as the FSK. An RF signal inputted from an antenna is amplified by a LNA 101. Thereafter, the RF signal is mixed with a local signal 103 in the mixer 102, and then is converted into an IF signal. Frequency components of the IF signal are attenuated except for the desired wave at a BPF (Band pass Filter) 104. After the IF signal is outputted from the BPF, the output amplitude of the IF signal becomes constant through a limiter amp or an AGC circuit 105, before the IF signal is outputted from the amp or the circuit. This output is divided into two, and one is inputted to a demodulation circuit mixer 106, and the other is inputted to a phase circuit 107 so as to rotate the phase by 90°. The output of the phase circuit 107 and the output of the AGC circuit 105 are inputted to the demodulation circuit mixer 106 and then multiplied by each other so as to output an analog demodulation signal. The multiplication generates high frequency signals or carrier components in the analog demodulation signal, and these signals or components are removed by a LPF (Low Pass Filter) 108. This analog demodulation output of the LPF 108 is digitalized in a data slicer circuit 109.

#FIG. 19 shows an example of a conventional data slicer circuit using an integration circuit. A demodulated signal outputted from a demodulator 202 is divided into two, and one is inputted to a comparator 203, and the other is inputted to the LPF 204 so as to remove an AC component so that only a DC component is outputted. This output from the LPF is connected to the other input end of the comparator 203. The comparator 203 digitalizes the demodulated signal by carrying out voltage comparison between the demodulated signal and the DC voltage component of the demodulated signal.

#FIG. 20 is an example of a conventional data slicer circuit including a differentiation circuit. A signal outputted from a demodulator 212 is inputted to a differentiation circuit 219, and the differentiation circuit 219 outputs a signal of either plus or minus polarity, which is then inputted to a comparator, so as to carry out digitalization.