High speed data transmitter and transmitting method thereof
AssigneeVIA Technologies, Inc.
InventorChi Chang
Life of this patent
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Abstract
A transmitter for transmitting data in response to N clock signals with the same period T is provided. Every two adjacent clock signals have a phase difference of T/N therebetween. The transmitter includes a clock synthesizer and a multiplexer. The clock synthesizer sequentially generates N select signals in response to level-switch states of the N clock signals, respectively, during the period T. The multiplexer is electrically connected to the clock synthesizer for selecting one of N input data signals to be outputted in response to a corresponding one of the N select signals in turn. A method for transmitting data with eliminated duty-cycle effect is also disclosed.
Claims16
A transmitter for transmitting data in response to N clock signals with the same period T, every two adjacent clock signals having a phase difference of T/N therebetween, said transmitter comprising:
- a clock synthesizer sequentially generating N select signals in response to level-switch states of said N clock signals, respectively, during said period T;
- and
- a multiplexer electrically connected to said clock synthesizer for selecting one of N input data signals to be outputted in response to a corresponding one of said N select signals in turn.
A transmitter for transmitting data in response to N clock signals derived from a reference clock signal of a first period, comprising:
- a clock synthesizer sequentially generating N select signals in response to said N clock signals, respectively, during a second period correlating to said first period of said reference clock signal;
- and
- a multiplexer electrically connected to said clock synthesizer and receiving N input data signals, wherein said N input data signals are sequentially selected to be outputted in response to said N select signals sequentially generated, respectively.
A method for transmitting data comprising steps of:
- providing N clock signals in response to a reference clock signal of a first period;
- sequentially generating N select signals in response to said N clock signals, respectively, during a second period correlating to said first period of said reference clock signal;
- and
- receiving N input data signals, wherein said N input data signals are sequentially selected to be outputted in response to said N select signals sequentially generated, respectively.
Dependencies are inferred from the claim text.