Method and apparatus for memory efficient compressed domain video processing
AssigneeSeiko Epson Corporation
InventorsWilliam Chen, Vasudev Bhaskaran
Life of this patent
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Abstract
A method for reducing the memory requirements for decoding a bit stream is provided. The method initiates with receiving a video bit stream. Then, a frame of the bit stream is decoded into a discrete cosine transform (DCT) domain representation. Next, non-zero coefficients of the DCT domain representation are identified. Then, a hybrid data structure is assembled. The hybrid data structure includes a fixed size array and a variable size overflow vector. Next, the non-zero coefficients of the DCT domain representation are inserted into the hybrid data structure. A computer readable media, a printed circuit board and a device configured to decode video data are also provided.
Claims30
A method for reducing the memory requirements for decoding a bit stream, comprising:
- receiving a video bit stream;
- decoding a frame of the bit stream into a transform domain representation;
- identifying non-zero coefficients of the transform domain representation;
- assembling a hybrid data structure including a fixed size array and a variable size overflow vector;
- and
- inserting the non-zero coefficients of the transform domain representation into the hybrid data structure.
A method for decoding video data, comprising:
- receiving a frame of video data within a compressed bit stream;
- decoding a block of the frame into a transform domain representation in the compressed domain;
- defining a hybrid data structure;
- storing data associated with the transform domain representation in the hybrid data structure;
- performing inverse motion compensation on the data associated with the transform domain representation in the compressed domain;
- and
- after performing the inverse motion compensation on the data, decompressing the data for display.
A computer readable media having program instructions for rearranging low rate bit stream data for storage into a hybrid data structure, comprising:
- program instructions for identifying non-zero transform coefficients associated with a coded block of a frame of data;
- program instructions for arranging the non-zero transform coefficients into a fixed size array;
- program instructions for determining if a quantity of the non-zero transform coefficients exceed a capacity of the fixed size array;
- program instructions for storing the non-zero transform coefficients exceeding the capacity of the fixed size array in a variable size overflow vector;
- and
- program instructions for translating the non-zero transform coefficients from a compressed domain to a spatial domain.
A circuit, comprising:
- a video decoder integrated circuit chip, the video decoder integrated circuit chip including,
- circuitry for receiving a bit stream of data associated with a frame of video data;
- circuitry for decoding the bit stream of data into a transform domain representation;
- circuitry for arranging non-zero transform coefficients of the transform domain representation in a hybrid data structure in a memory associated with the video decoder;
- and
- circuitry for decompressing the non-zero transform coefficients of the transform domain representation for display.
A device configured to display a video image, comprising:
- a central processing unit (CPU);
- a random access memory (RAM);
- a display screen configured to present an image;
- decoder circuitry configured to transform a video bit stream into a transform domain representation, the decoder circuitry capable of arranging non-zero transform coefficients of the transform domain representation in a hybrid data structure in a memory associated with the decoder circuitry, the decoder circuitry including circuitry for selectively applying a hybrid factorization/integer approximation technique during inverse motion compensation;
- and
- a bus in communication with the CPU, the RAM, the display screen and the decoder circuitry.
Dependencies are inferred from the claim text.