Method and system for embedding a first clock signal phase within a second signal

#1. Technical Field of the Invention

#The present invention generally relates to signaling server timing distribution. More particularly, and not by way of any limitation, the present invention is directed to a method and system for embedding the phase of a first clock signal within a second signal.

#2. Description of Related Art

#A more complete understanding of the present invention may be had by reference to the following Detailed Description when taken in conjunction with the accompanying drawings wherein:

#FIG. 1 is a high level functional block diagram of a system in accordance with one embodiment of the invention for embedding the phase of one clock signal within another signal;

#FIG. 2 is a more detailed functional block diagram of the system of FIG. 1 for embedding the phase of a first clock signal within a second signal;

#In the drawings, like or similar elements are designated with identical reference numerals throughout the several views thereof, and the various elements depicted are not necessarily drawn to scale.

#FIG. 1 is a high level block diagram of a system 100 in accordance with one embodiment of the invention for embedding the phase of one clock signal within another signal. A building integrated timing source 102 provides a reference signal, for example, a 64 KHz composite clock signal, to a system timing generator (“STG”) 104. As will be described in greater detail below, the STG 104 generates and distributes a set of filtered clock signals to be used as the general purpose clock within telecommunications equipment, represented in FIG. 1 by data transmission modules 108A-108C, located at the site. In a preferred embodiment, the modules 108A-108C comprise telecommunications interface modules. It will be assumed that one of the modules, e.g., module 108A, is a DS0 interface module, while the others (e.g., modules 108B and 108C) are non-DS0 (e.g., DS1 or E1) interface modules.

#As will be recognized by one of ordinary skill in the art, the module 108A will have different timing requirements than those of the modules 108B, 108C; namely, data transmitted via the module 108A is required to follow the composite clock, while the modules 108B and 108C require a highly filtered clock in order to function properly.