Data link/physical layer packet diversion and insertion

A networking apparatus comprising:

• a switching fabric including a plurality of ingress/egress points to switch routing paths of packets received through mediums coupled to the ingress/egress points;
• a first buffering structure including a first plurality of storage structures and first associated packet diversion and insertion logic, coupled to a first of said ingress/egress points to facilitate at least a selected one of diversion of selected ones of a first plurality of ingress packets being received from a first one of said mediums into said switching fabric through said first ingress/egress point, and insertion of additional ones into said first plurality of ingress packets being received;
• and
• a second buffering structure including a second plurality of storage structures and second associated packet diversion and insertion logic, coupled to a second of said ingress/egress points to facilitate at least a selected one of diversion of selected ones of a second plurality of ingress packets being received from a second one of said mediums into said switching fabric through said second ingress/egress point, and insertion of additional ones into said second plurality of ingress packets being received.

A networking apparatus comprising:

• a switching fabric including a plurality of ingress/egress points to switch packets received through mediums coupled to the ingress/egress points;
• and
• a buffering structure including
• a first plurality of storage structures and first associated packet diversion and insertion logic, coupled to a first of said ingress/egress points, to facilitate at least a selected one of diversion of selected ones of a plurality of ingress packets being received from a first one of said mediums into said switching fabric through said first ingress/egress point, and insertion of additional ones into said plurality of ingress packets being received, and
• a second buffering structure including a second plurality of storage structures and second associated packet diversion and insertion logic, coupled to the first ingress/egress point, to facilitate at least a selected one of diversion of selected ones of a plurality of egress packets being routed through said first ingress/egress point onto said first medium, and insertion of additional ones into said plurality of ingress packets being routed.

An optical networking module comprising:

• an optical component to send and receive optical signals encoded with data transmitted through a coupled optical medium;
• an optical-electrical component coupled to the optical component to encode digital data onto optical signals and to decode encoded digital data on optical signals back into their digital forms;
• a data link/physical layer processing unit, including a buffering structure comprising a plurality of storage structures and associated packet diversion and insertion logic, coupled to the optical-electrical component and to a packet source/sink, to facilitate at least a selected one of data link/physical processing of ingress packets received from said optical medium for said packet source/sink and egress packets to be routed from said packet source/sink onto said optical medium, with each of said data link/physical processing of ingress and egress packets including at least a selected one of diversion of selected ones of a plurality of ingress/egress packets being received from/routed onto said optical medium, and insertion of additional ones into said plurality of ingress/egress packets being received/routed;
• and
• a body encasing said optical component, said optical-electrical component, and said data link/physical processing unit as a single module.

A multi-protocol processor comprising:

• a plurality of I/O interfaces to facilitate selective optical-electrical trafficking of data transmitted in accordance with a selected one of a plurality of datacom and telecom protocols;
• a plurality of data link and physical sub-layer processing units selectively coupled to each other and to the I/O interfaces to be selectively employed in combination to perform selected data link and physical sub-layer processing on egress as well as ingress ones of said data, in accordance with said selected one of said plurality of protocols;
• and
• a buffering structure coupled to at least a system-side one of said I/O interfaces and a media processing one of said data link and physical sub-layer processing units, including a plurality of storage structures and associated packet diversion and insertion logic to facilitate at least a selected one of diversion of selected ones of a plurality of egress packets, and insertion of additional ones into said plurality of egress packets, diversion of selected ones of a plurality of ingress packets, and insertion of additional ones into said plurality of ingress packets.

A buffering structure comprising:

• a first storage structure to stage undiverted ones of egress packets;
• a second storage structure to stage diverted ones of egress packets;
• a third storage structure to stage insertion ones of egress packets;
• a first divert logic coupled to said first and second storage structures to selectively route egress packets onto a selected one of said first and second storage structures;
• a first insert logic coupled to said first and third storage structures to selectively merge said undiverted ones and said insertion ones of said egress packets;
• and
• a register interface, including packet packing and unpacking logic, coupled to the second and third storage structures to facilitate retrieval by a processor said diverted ones of said egress packets in unpacked portions, and provision by said processor said insertion ones of said egress packets in unpacked portions.

A buffering structure comprising:

• a first storage structure to stage undiverted ones of ingress packets;
• a second storage structure to stage diverted ones of ingress packets;
• a third storage structure to stage insertion ones of ingress packets;
• a first divert logic coupled to said first and second storage structures to selectively route ingress packets onto a selected one of said first and second storage structures;
• a first insert logic coupled to said first and third storage structures to selectively merge said undiverted ones and said insertion ones of said ingress packets;
• and
• a register interface, including packet packing and unpacking logic, coupled to the second and third storage structures to facilitate retrieval by a processor said diverted ones of said ingress packets in unpacked portions, and provision by said processor said insertion ones of said ingress packets in unpacked portions.

A buffering structure comprising:

• a first storage structure to stage undiverted ones of ingress packets;
• a second storage structure to stage diverted ones of ingress packets;
• a third storage structure to stage undiverted ones of egress packets;
• a fourth storage structure to stage diverted ones of egress packets;
• a first divert logic coupled to said first and second storage structures to selectively route ingress packets onto a selected one of said first and second storage structures;
• a second divert logic coupled to said third and fourth storage structures to selectively route egress packets onto a selected one of said third and fourth storage structures;
• and
• a register interface, including packet unpacking logic, coupled to the second and fourth storage structures to facilitate retrieval by a processor said diverted ones of said ingress and egress packets in unpacked portions.

A buffering structure comprising:

• a first storage structure to stage undiverted ones of ingress packets;
• a second storage structure to stage insertion ones of ingress packets;
• a third storage structure to stage undiverted ones of egress packets;
• a fourth storage structure to stage insertion ones of egress packets;
• a first insertion logic coupled to the first and second storage structures to selective merge said undiverted ones and said insertion ones of said ingress packets;
• a second insertion logic coupled to the third and fourth storage structures to selective merge said undiverted ones and said insertion ones of said egress packets;
• and
• a register interface, including packet packing logic, coupled to the second and fourth storage structures to facilitate provision by a processor said insertion ones of said ingress and egress packets in unpacked portions.