Controlled shared memory smart switch system

3) An interconnect structure comprising a plurality of input ports and a plurality of output ports with a message M being sent from an input port to a predetermined output port through a switch S, said message M consisting of a header segment and a data segment, wherein the setting of switch S is not dependent upon the header segment of message M.

10) An interconnect structure comprising a plurality of input ports and a plurality of output ports, and wherein logic associated with an input port stores a message M in a data storage unit U and logic associated with an output port OP of said interconnect structure is used in moving message M from data storage unit U to output port OP.

15) An interconnect structure comprising a plurality of input ports and a plurality of out ports and a plurality of messages M being sent from said plurality of input ports to said plurality of output ports, each of said messages M having a predetermined status within said interconnect structure, said interconnect structure further comprising logic associated with an output port OP which informs said plurality of input ports of said status of messages M within said interconnect structure, for messages M which are targeted for output port OP.

18) An interconnect structure A having at least one input port IP with a logic L being associated with said input port IP, and at least one output port OP, said interconnect structure having a plurality of output lines L0, L1-LJ−1 for sending a message M to a device BP, wherein when message M targeted for BP arrives at IP, said logic L chooses an output port OP associated with one of said output lines to receive message M.

22) An interconnect structure comprising a plurality of input ports and a plurality of output ports with a message M being sent from an input port to a predetermined output port, said interconnect structure further including logic for generating control data, said control data being carried on paths within said interconnect structure separate from paths carrying said message M.

24) A method of sending control information through a plurality of separate devices in an interconnect structure comprising the steps of transmitting a message M from a plurality of input ports to a plurality of output ports, generating control information from logic associated with one of said input ports B and sending said control information to logic associated with one of said output ports A on a path separate from message M.